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1. 发明授权

US06962847B2 Method for forming a self-aligned buried strap in a vertical memory cell 有权
标题翻译：在垂直存储单元中形成自对准掩埋带的方法
公开(公告)号：US06962847B2
公开(公告)日：2005-11-08
申请号：US10846321
申请日：2004-05-14
申请人： Cheng-Chih Huang , Sheng-Wei Yang , Neng-Tai Shih , Chen-Chou Huang
发明人： Cheng-Chih Huang , Sheng-Wei Yang , Neng-Tai Shih , Chen-Chou Huang
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/20
CPC分类号： H01L28/40 , H01L27/10864 , H01L27/10867
摘要： A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided. A collar dielectric layer is conformally formed on the trench bottom portion, and the trench is filled with a conducting layer. The collar dielectric layer is etched below the level of the surface of the conducting layer to form a groove between the conducting layer and the trench. The groove is filled with a doped conducting layer. The dopant in the doped conducting layer is diffused to the semiconductor substrate in an ion diffusion area as a buried strap. The conducting layer and the doped conducting layer are etched below the ion diffusion area. A top trench insulating layer is formed on the bottom of the trench, wherein the top trench insulating layer is lower than the ion diffusion area.
摘要翻译：一种用于在垂直存储单元中形成自对准埋置带的方法。提供具有沟槽的半导体衬底。轴环电介质层共形地形成在沟槽底部上，并且沟槽填充有导电层。在导电层的表面的水平面下蚀刻套环电介质层，以在导电层和沟槽之间形成凹槽。凹槽填充有掺杂的导电层。掺杂导电层中的掺杂剂作为掩埋带扩散到离子扩散区域中的半导体衬底。导电层和掺杂导电层被蚀刻在离子扩散区下面。在沟槽的底部形成顶部沟槽绝缘层，其中顶部沟槽绝缘层低于离子扩散区域。

2. 发明授权

US06927123B2 Method for forming a self-aligned buried strap in a vertical memory cell 有权
标题翻译：在垂直存储单元中形成自对准掩埋带的方法
公开(公告)号：US06927123B2
公开(公告)日：2005-08-09
申请号：US10846272
申请日：2004-05-14
申请人： Cheng-Chih Huang , Sheng-Wei Yang , Neng-Tai Shih , Chen-Chou Huang
发明人： Cheng-Chih Huang , Sheng-Wei Yang , Neng-Tai Shih , Chen-Chou Huang
IPC分类号： H01L21/02 , H01L21/8242 , H01L29/94 , H01L21/20
CPC分类号： H01L28/40 , H01L27/10864 , H01L27/10867 , H01L29/945
摘要： A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided, a capacitor wire is formed on the bottom portion of the trench, and a collar dielectric layer is formed between the capacitor wire and the semiconductor substrate to act as an isolation. The capacitor wire and the collar dielectric layer are etched to a predetermined depth, such that a gap is formed between the spacer and the capacitor wire and the collar dielectric layer. Ions are doped into the exposed semiconductor substrate to form an ion doped area acting as a buried strap. The spacer is removed, and an exposed collar dielectric layer is etched below the level of the surface of the capacitor wire, and a groove is formed between the capacitor wire and the trench sidewall to fill with a conducting layer.
摘要翻译：一种用于在垂直存储单元中形成自对准埋置带的方法。提供具有沟槽的半导体衬底，在沟槽的底部形成电容器线，并且在电容器布线和半导体衬底之间形成环形电介质层以作为隔离。电容器线和套环电介质层被蚀刻到预定深度，使得在间隔物和电容器线和套环电介质层之间形成间隙。将离子掺杂到暴露的半导体衬底中以形成充当掩埋带的离子掺杂区域。去除间隔物，并且暴露的环形介电层被蚀刻到电容器线的表面的水平面以下，并且在电容器布线和沟槽侧壁之间形成凹槽以填充导电层。

3. 发明申请

US20050124110A1 METHOD FOR FORMING A SELF-ALIGNED BURIED STRAP IN A VERTICAL MEMORY CELL 有权
标题翻译：用于在垂直存储器单元中形成自对准的BURIED STRAP的方法
公开(公告)号：US20050124110A1
公开(公告)日：2005-06-09
申请号：US10846272
申请日：2004-05-14
申请人： Cheng-Chih Huang , Sheng-Wei Yang , Neng-Tai Shih , Chen-Chou Huang
发明人： Cheng-Chih Huang , Sheng-Wei Yang , Neng-Tai Shih , Chen-Chou Huang
IPC分类号： H01L21/02 , H01L21/8242 , H01L29/94 , H01L21/8234 , H01L21/20 , H01L21/8244 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L28/40 , H01L27/10864 , H01L27/10867 , H01L29/945
摘要： A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided, a capacitor wire is formed on the bottom portion of the trench, and a collar dielectric layer is formed between the capacitor wire and the semiconductor substrate to act as an isolation. The capacitor wire and the collar dielectric layer are etched to a predetermined dept, such that a gap is formed between the spacer and the capacitor wire and the collar dielectric layer. Ions are doped into the exposed semiconductor substrate to form an ion doped area acting as a buried strap. The spacer is removed, and an exposed collar dielectric layer is etched below the level of the surface of the capacitor wire, and a groove is formed between the capacitor wire and the trench sidewall to fill with a conducting layer.
摘要翻译：一种用于在垂直存储单元中形成自对准埋置带的方法。提供具有沟槽的半导体衬底，在沟槽的底部形成电容器线，并且在电容器布线和半导体衬底之间形成环形电介质层以作为隔离。电容器线和套环电介质层被蚀刻到预定的部分，使得在间隔件和电容器线和套环电介质层之间形成间隙。将离子掺杂到暴露的半导体衬底中以形成充当掩埋带的离子掺杂区域。去除间隔物，并且暴露的环形介电层被蚀刻到电容器线的表面的水平面以下，并且在电容器布线和沟槽侧壁之间形成凹槽以填充导电层。

4. 发明申请

US20050124111A1 Method for forming a self-aligned buried strap in a vertical memory cell 有权
公开(公告)号：US20050124111A1
公开(公告)日：2005-06-09
申请号：US10846321
申请日：2004-05-14
申请人： Cheng-Chih Huang , Sheng-Wei Yang , Neng-Tai Shih , Chen-Chou Huang
发明人： Cheng-Chih Huang , Sheng-Wei Yang , Neng-Tai Shih , Chen-Chou Huang
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/8238 , H01L21/20 , H01L21/8234 , H01L21/8244
CPC分类号： H01L28/40 , H01L27/10864 , H01L27/10867
摘要： A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided. A collar dielectric layer is conformally formed on the trench bottom portion, and the trench is filled with a conducting layer. The collar dielectric layer is etched below the level of the surface of the conducting layer to form a groove between the conducting layer and the trench. The groove is filled with a doped conducting layer. The dopant in the doped conducting layer is diffused to the semiconductor substrate in an ion diffusion area as a buried strap. The conducting layer and the doped conducting layer are etched below the ion diffusion area. A top trench insulating layer is formed on the bottom of the trench, wherein the top trench insulating layer is lower than the ion diffusion area.

5. 发明申请

US20050064643A1 Method for isolation layer for a vertical DRAM 有权
标题翻译：垂直DRAM隔离层方法
公开(公告)号：US20050064643A1
公开(公告)日：2005-03-24
申请号：US10943699
申请日：2004-09-17
申请人： Cheng-Chih Huang , Sheng-Wei Yang , Chen-Chou Huang , Sheng-Tsung Chen
发明人： Cheng-Chih Huang , Sheng-Wei Yang , Chen-Chou Huang , Sheng-Tsung Chen
IPC分类号： H01L21/8238 , H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10876
摘要： A method for forming isolation layer in a vertical DRAM. A semiconductor substrate with a plurality of first trenches is provided, with a collar dielectric layer is formed on a sidewall of each, and each filled with a first conducting layer. A patterned mask layer is formed on the semiconductor substrate, and the semiconductor substrate is etched using the patterned mask layer as an etching mask to form a plurality of second trenches. The patterned mask layer is removed. Each second trench is filled with an insulating layer acting as an isolation. Each of first conducting layers is etched to form a plurality of grooves. A doped area acting as a buried strap is formed in the semiconductor substrate beside each groove. A trench top insulating layer is formed in the bottom surface of each trench. Each first trench is filled with a second conducting layer acting as a gate.
摘要翻译：一种用于在垂直DRAM中形成隔离层的方法。提供了具有多个第一沟槽的半导体衬底，其中，在每个的侧壁上形成一个环形电介质层，并且各自填充有第一导电层。在半导体衬底上形成图案化掩模层，并使用图案化掩模层作为蚀刻掩模蚀刻半导体衬底，以形成多个第二沟槽。去除图案化的掩模层。每个第二沟槽填充有用作隔离层的绝缘层。每个第一导电层被蚀刻以形成多个凹槽。在每个沟槽旁边的半导体衬底中形成用作掩埋带的掺杂区域。沟槽顶部绝缘层形成在每个沟槽的底表面中。每个第一沟槽填充有用作栅极的第二导电层。

6. 发明授权

US07074700B2 Method for isolation layer for a vertical DRAM 有权
标题翻译：垂直DRAM隔离层方法
公开(公告)号：US07074700B2
公开(公告)日：2006-07-11
申请号：US10943699
申请日：2004-09-17
申请人： Cheng-Chih Huang , Sheng-Wei Yang , Chen-Chou Huang , Sheng-Tsung Chen
发明人： Cheng-Chih Huang , Sheng-Wei Yang , Chen-Chou Huang , Sheng-Tsung Chen
IPC分类号： H01L21/22
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10876
摘要： A method for forming isolation layer in a vertical DRAM. A semiconductor substrate with a plurality of first trenches is provided, with a collar dielectric layer is formed on a sidewall of each, and each filled with a first conducting layer. A patterned mask layer is formed on the semiconductor substrate, and the semiconductor substrate is etched using the patterned mask layer as an etching mask to form a plurality of second trenches. The patterned mask layer is removed. Each second trench is filled with an insulating layer acting as an isolation. Each of first conducting layers is etched to form a plurality of grooves. A doped area acting as a buried strap is formed in the semiconductor substrate beside each groove. A trench top insulating layer is formed in the bottom surface of each trench. Each first trench is filled with a second conducting layer acting as a gate.
摘要翻译：一种用于在垂直DRAM中形成隔离层的方法。提供了具有多个第一沟槽的半导体衬底，其中，在每个的侧壁上形成一个环形电介质层，并且各自填充有第一导电层。在半导体衬底上形成图案化掩模层，并使用图案化掩模层作为蚀刻掩模蚀刻半导体衬底，以形成多个第二沟槽。去除图案化的掩模层。每个第二沟槽填充有用作隔离层的绝缘层。每个第一导电层被蚀刻以形成多个凹槽。在每个沟槽旁边的半导体衬底中形成用作掩埋带的掺杂区域。沟槽顶部绝缘层形成在每个沟槽的底表面中。每个第一沟槽填充有用作栅极的第二导电层。

7. 发明申请

US20050016948A1 Method for fabricating trench isolations with high aspect ratio 有权
公开(公告)号：US20050016948A1
公开(公告)日：2005-01-27
申请号：US10690999
申请日：2003-10-22
申请人： Sheng-Wei Yang , Neng-Tai Shih , Wen-Sheng Liao , Chih-How Chang
发明人： Sheng-Wei Yang , Neng-Tai Shih , Wen-Sheng Liao , Chih-How Chang
IPC分类号： H01L21/3105 , H01L21/311 , H01L21/316 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/31053 , H01L21/31116 , H01L21/31612 , H01L21/76232
摘要： A method of fabricating a trench isolation with high aspect ratio. The method comprises the steps of: providing a substrate with a trench; depositing a first isolation layer filling the trench by low pressure chemical vapor deposition; etching the first isolation layer so that its surface is lowered to the opening of the trench; depositing a second isolation layer to fill the trench without voids by high density plasma chemical vapor deposition and achieving global planarization by chemical-mechanical polishing then providing a rapidly annealing procedure. Accordingly, the present invention achieves void-free trench isolation with high aspect ratio.

8. 发明授权

US06946359B2 Method for fabricating trench isolations with high aspect ratio 有权
标题翻译：用于制造具有高纵横比的沟槽隔离的方法
公开(公告)号：US06946359B2
公开(公告)日：2005-09-20
申请号：US10690999
申请日：2003-10-22
申请人： Sheng-Wei Yang , Neng-Tai Shih , Wen-Sheng Liao , Chih-How Chang
发明人： Sheng-Wei Yang , Neng-Tai Shih , Wen-Sheng Liao , Chih-How Chang
IPC分类号： H01L21/3105 , H01L21/311 , H01L21/316 , H01L21/762 , H01L21/302
CPC分类号： H01L21/76224 , H01L21/31053 , H01L21/31116 , H01L21/31612 , H01L21/76232
摘要： A method of fabricating a trench isolation with high aspect ratio. The method comprises the steps of: providing a substrate with a trench; depositing a first isolation layer filling the trench by low pressure chemical vapor deposition; etching the first isolation layer so that its surface is lowered to the opening of the trench; depositing a second isolation layer to fill the trench without voids by high density plasma chemical vapor deposition and achieving global planarization by chemical-mechanical polishing then providing a rapidly annealing procedure. Accordingly, the present invention achieves void-free trench isolation with high aspect ratio.
摘要翻译：一种制造具有高纵横比的沟槽隔离的方法。该方法包括以下步骤：为衬底提供沟槽; 通过低压化学气相沉积沉积填充沟槽的第一隔离层; 蚀刻第一隔离层使得其表面降低到沟槽的开口; 沉积第二隔离层以通过高密度等离子体化学气相沉积而填充沟槽而无空隙，并通过化学机械抛光实现全局平坦化，然后提供快速退火工艺。因此，本发明实现了具有高纵横比的无空隙沟槽隔离。

9. 发明申请

US20050014331A1 PROCESS FOR PLANARIZING ARRAY TOP OXIDE IN VERTICAL MOSFET DRAM ARRAYS 有权
标题翻译：在垂直MOSFET DRAM阵列中平面排列顶部氧化物的方法
公开(公告)号：US20050014331A1
公开(公告)日：2005-01-20
申请号：US10604361
申请日：2003-07-14
申请人： Sheng-Wei Yang , Cheng-Chih Huang , Chien-Mao Liao
发明人： Sheng-Wei Yang , Cheng-Chih Huang , Chien-Mao Liao
IPC分类号： H01L21/3105 , H01L21/311 , H01L21/316 , H01L21/8242 , H01L21/8234
CPC分类号： H01L27/10894 , H01L21/31053 , H01L21/31056 , H01L21/31111 , H01L21/31612 , H01L27/10864
摘要： The present invention provides a process for planarizing array top oxide (ATO) in vertical MOSFET DRAM arrays. In contrast to the prior art ARC-RIE planarization method for EA/ES (etch array/etch support) module, the present invention takes advantage of chemical mechanical polishing (CMP) technique to overcome residue problems that used to occur at the transition region or array edge. It might cause capacitor device failure when ATO residue is left on the transition region.
摘要翻译：本发明提供了一种在垂直MOSFET DRAM阵列中平面化阵列顶部氧化物（ATO）的方法。与用于EA / ES（蚀刻阵列/蚀刻支持）模块的现有技术的ARC-RIE平面化方法相反，本发明利用化学机械抛光（CMP）技术来克服在过渡区域发生的残留问题，阵列边缘。当ATO残留物留在过渡区域时，可能会导致电容器故障。

10. 发明授权

US06958283B2 Method for fabricating trench isolation 有权
公开(公告)号：US06958283B2
公开(公告)日：2005-10-25
申请号：US10690859
申请日：2003-10-22
申请人： Chien-Mao Liao , Tzu-En Ho , Chang-Rong Wu , Chih-How Chang , Sheng-Wei Yang , Sheng-Tsung Chen , Chung-Yuan Lee , Wen-Sheng Liao , Chen-Chou Huang
发明人： Chien-Mao Liao , Tzu-En Ho , Chang-Rong Wu , Chih-How Chang , Sheng-Wei Yang , Sheng-Tsung Chen , Chung-Yuan Lee , Wen-Sheng Liao , Chen-Chou Huang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229
摘要： A method for forming a trench isolation. A semiconductor substrate with an opening is provided, on which a mask layer is formed. A first insulating layer is conformably formed on the semiconductor substrate and the trench, and the trench is filled with the first insulating layer. The first insulating layer is anisotropically etched to below the semiconductor substrate. A second insulating layer is formed on the semiconductor substrate and the trench. The second insulating layer is planarized to expose the mask layer.

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