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1. 发明授权

US09099556B2 Transistor having an active region with wing structure 有权
标题翻译：晶体管具有机翼结构的有源区域
公开(公告)号：US09099556B2
公开(公告)日：2015-08-04
申请号：US13213409
申请日：2011-08-19
申请人： Chen-Liang Chu , Fei-Yuh Chen , Yi-Sheng Chen , Shih-Kuang Hsiao , Chun Lin Tsai , Kong-Beng Thei
发明人： Chen-Liang Chu , Fei-Yuh Chen , Yi-Sheng Chen , Shih-Kuang Hsiao , Chun Lin Tsai , Kong-Beng Thei
IPC分类号： H01L29/76 , H01L29/78 , H01L29/10 , H01L29/06
CPC分类号： H01L29/41775 , H01L29/0653 , H01L29/0692 , H01L29/1033 , H01L29/1045 , H01L29/78 , H01L29/7823 , H01L29/7835
摘要： A semiconductor device includes an active region having a channel region and at least a wing region adjoining the channel region under the gate dielectric layer. The at least one wing region may be two symmetrical wing regions across the channel region.
摘要翻译：半导体器件包括具有通道区域的有源区域和与栅极介电层下方的沟道区域邻接的至少一个翼区域。所述至少一个机翼区域可以是穿过所述通道区域的两个对称翼区域。

2. 发明授权

US10014291B2 SiC crystalline on Si substrates to allow integration of GaN and Si electronics 有权
公开(公告)号：US10014291B2
公开(公告)日：2018-07-03
申请号：US13760496
申请日：2013-02-06
申请人： Kong-Beng Thei , Jiun-Lei Jerry Yu , Chun Lin Tsai , Hsiao-Chin Tuan , Alex Kalnitsky
发明人： Kong-Beng Thei , Jiun-Lei Jerry Yu , Chun Lin Tsai , Hsiao-Chin Tuan , Alex Kalnitsky
IPC分类号： H01L29/15 , H01L27/06 , H01L21/8258 , H01L27/085 , H01L21/265
CPC分类号： H01L27/0617 , H01L21/26506 , H01L21/8258 , H01L27/085 , H01L2924/0002 , H01L2924/00
摘要： A silicon substrate with a GaN-based device and a Si-based device on the silicon substrate is provided. The silicon substrate includes the GaN-based device on a SiC crystalline region. The SiC crystalline region is formed in the silicon substrate. The silicon substrate also includes the Si-based device on a silicon region, and the silicon region is next to the SiC crystalline region on the silicon substrate.

3. 发明授权

US08389348B2 Mechanism of forming SiC crystalline on Si substrates to allow integration of GaN and Si electronics 有权
标题翻译：在Si衬底上形成SiC晶体以允许GaN和Si电子器件集成的机理
公开(公告)号：US08389348B2
公开(公告)日：2013-03-05
申请号：US12881505
申请日：2010-09-14
申请人： Kong-Beng Thei , Jiun-Lei Jerry Yu , Chun Lin Tsai , Hsiao-Chin Tuan , Alex Kalnitsky
发明人： Kong-Beng Thei , Jiun-Lei Jerry Yu , Chun Lin Tsai , Hsiao-Chin Tuan , Alex Kalnitsky
IPC分类号： H01L21/338
CPC分类号： H01L27/0617 , H01L21/26506 , H01L21/8258 , H01L27/085 , H01L2924/0002 , H01L2924/00
摘要： The mechanisms of forming SiC crystalline regions on Si substrate described above enable formation and integration of GaN-based devices and Si-based devices on a same substrate. The SiC crystalline regions are formed by implanting carbon into regions of Si substrate and then annealing the substrate. An implant-stop layer is used to cover the Si device regions during formation of the SiC crystalline regions.
摘要翻译：在上述Si衬底上形成SiC结晶区的机理能够在同一衬底上形成GaN和GaN基器件的集成。通过将碳注入到Si衬底的区域中，然后使衬底退火来形成SiC晶体区域。在形成SiC晶体区域期间，使用注入停止层来覆盖Si器件区域。

4. 发明授权

US08803232B2 High voltage and ultra-high voltage semiconductor devices with increased breakdown voltages 有权
标题翻译：具有增加的击穿电压的高压和超高压半导体器件
公开(公告)号：US08803232B2
公开(公告)日：2014-08-12
申请号：US13186660
申请日：2011-07-20
申请人： Ker Hsiao Huo , Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng
发明人： Ker Hsiao Huo , Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng
IPC分类号： H01L29/66 , H01L29/40 , H01L29/08 , H01L29/78
CPC分类号： H01L29/404 , H01L29/0607 , H01L29/0615 , H01L29/0649 , H01L29/0696 , H01L29/0852 , H01L29/0869 , H01L29/0886 , H01L29/1095 , H01L29/402 , H01L29/41758 , H01L29/4238 , H01L29/49 , H01L29/66674 , H01L29/66681 , H01L29/7801 , H01L29/7816
摘要： A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.
摘要翻译：横向DMOS晶体管设置有源极区，漏极区和导电栅。漏极区域通过在导电栅极下方侵入的场氧化物与导电栅极横向分离。横向DMOS晶体管可以形成为跑道状结构，其中导电栅极包括直线部分和弯曲部分并被源极区域包围。布置在导电栅极和捕获的漏极之间是一层或多层次的层间电介质材料。一组或多组隔离的导体引线形成在电介质层中或介质层上，并且可以设置在多个器件级。隔离导电引线增加了横向DMOS晶体管的击穿电压，特别是在电场拥挤可能会降低击穿电压的弯曲区域中。

5. 发明授权

US08680616B2 High side gate driver device 有权
标题翻译：高边栅驱动器
公开(公告)号：US08680616B2
公开(公告)日：2014-03-25
申请号：US12959538
申请日：2010-12-03
申请人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Ker Hsiao Huo , Chih-Chang Cheng , Ruey-Hsin Liu
发明人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Ker Hsiao Huo , Chih-Chang Cheng , Ruey-Hsin Liu
IPC分类号： H01L21/00
CPC分类号： H01L29/7816 , H01L21/76202 , H01L27/0629 , H01L29/0696 , H01L29/1095 , H01L29/42368 , H01L29/861
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region.
摘要翻译：本发明提供一种半导体器件。半导体器件包括：漂移区，其具有形成在衬底中的第一掺杂极性; 掺杂的延伸区域形成在所述漂移区域中，并且具有与所述第一掺杂极性相反的第二掺杂极性，所述掺杂延伸区域包括横向延伸的部件; 在所述漂移区上形成的电介质结构，所述电介质结构通过所述漂移区的一部分与所述掺杂延伸区分离; 形成在电介质结构的一部分上的栅结构和掺杂延伸区的一部分; 以及具有第二掺杂极性的掺杂隔离区，所述掺杂隔离区至少部分地围绕所述漂移区和所述掺杂延伸区。

6. 发明授权

US08587073B2 High voltage resistor 有权
公开(公告)号：US08587073B2
公开(公告)日：2013-11-19
申请号：US12905840
申请日：2010-10-15
申请人： Chih-Chang Cheng , Ruey-Hsin Liu , Chih-Wen (Albert) Yao , Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai
发明人： Chih-Chang Cheng , Ruey-Hsin Liu , Chih-Wen (Albert) Yao , Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai
IPC分类号： H01L23/62
CPC分类号： H01L29/66166 , H01L23/5228 , H01L27/0288 , H01L27/0802 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities.

7. 发明申请

US20120319240A1 High Voltage Resistor With Pin Diode Isolation 有权
标题翻译：高压电阻与引脚二极管隔离
公开(公告)号：US20120319240A1
公开(公告)日：2012-12-20
申请号：US13160030
申请日：2011-06-14
申请人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng , Ruey-Hsin Liu
发明人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng , Ruey-Hsin Liu
IPC分类号： H01L29/8605 , H01L21/20
CPC分类号： H01L29/0649 , H01L21/26513 , H01L21/74 , H01L21/761 , H01L21/76202 , H01L23/528 , H01L27/0676 , H01L27/0802 , H01L28/20 , H01L29/0692 , H01L29/456 , H01L29/6609 , H01L29/8605 , H01L29/868
摘要： Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.
摘要翻译：提供一种高压半导体器件，其包括形成在衬底中的PIN二极管结构。 PIN二极管包括位于第一掺杂阱和第二掺杂阱之间的本征区。第一和第二掺杂阱具有与内部区域相反的掺杂极性和更大的掺杂浓度水平。半导体器件包括形成在第一掺杂阱的一部分上的绝缘结构。半导体器件包括形成在绝缘结构上的细长电阻器件。电阻器件分别设置在电阻器件的相对端处的第一和第二部分。半导体器件包括形成在电阻器件上的互连结构。互连结构包括：电耦合到第一掺杂阱的第一接触和电耦合到位于第一和第二部分之间的电阻器的第三部分的第二接触。

8. 发明申请

US20120091529A1 HIGH VOLTAGE RESISTOR 有权
标题翻译：高压电阻
公开(公告)号：US20120091529A1
公开(公告)日：2012-04-19
申请号：US12905840
申请日：2010-10-15
申请人： Chih-Chang Cheng , Ruey-Hsin Liu , Chih-Wen (Albert) Yao , Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai
发明人： Chih-Chang Cheng , Ruey-Hsin Liu , Chih-Wen (Albert) Yao , Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L29/66166 , H01L23/5228 , H01L27/0288 , H01L27/0802 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities.
摘要翻译：提供一种半导体器件。半导体器件包括电阻器和电压保护器件。电阻器具有螺旋形状。电阻器具有第一部分和第二部分。电压保护装置包括电耦合到电阻器的第一部分的第一掺杂区域。电压保护装置包括电耦合到电阻器的第二部分的第二掺杂区域。第一和第二掺杂区具有相反的掺杂极性。

9. 发明申请

US20140021560A1 HIGH VOLTAGE DEVICE WITH A PARALLEL RESISTOR 有权
标题翻译：具有并联电阻的高电压装置
公开(公告)号：US20140021560A1
公开(公告)日：2014-01-23
申请号：US13551262
申请日：2012-07-17
申请人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Ker Hsiao Huo , Jen-Hao Yeh , Chun-Wei Hsu
发明人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Ker Hsiao Huo , Jen-Hao Yeh , Chun-Wei Hsu
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0629
摘要： Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a transistor having a gate, a source, and a drain. The source and the drain are formed in a doped substrate and are separated by a drift region of the substrate. The gate is formed over the drift region and between the source and the drain. The transistor is configured to handle high voltage conditions that are at least a few hundred volts. The high voltage semiconductor device includes a dielectric structure formed between the source and the drain of the transistor. The dielectric structure protrudes into and out of the substrate. Different parts of the dielectric structure have uneven thicknesses. The high voltage semiconductor device includes a resistor formed over the dielectric structure. The resistor has a plurality of winding segments that are substantially evenly spaced apart.
摘要翻译：提供高压半导体器件。高电压半导体器件包括具有栅极，源极和漏极的晶体管。源极和漏极形成在掺杂衬底中并且由衬底的漂移区域分离。栅极形成在漂移区域上以及源极和漏极之间。晶体管被配置为处理至少几百伏特的高电压条件。高电压半导体器件包括在晶体管的源极和漏极之间形成的电介质结构。电介质结构突出进出基板。电介质结构的不同部分具有不均匀的厚度。高电压半导体器件包括在电介质结构上形成的电阻器。电阻器具有大致均匀间隔开的多个绕组段。

10. 发明授权

US08629026B2 Source tip optimization for high voltage transistor devices 有权
标题翻译：高压晶体管器件的源尖优化
公开(公告)号：US08629026B2
公开(公告)日：2014-01-14
申请号：US12944959
申请日：2010-11-12
申请人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng , Ruey-Hsin Liu
发明人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng , Ruey-Hsin Liu
IPC分类号： H01L21/22 , H01L21/331 , H01L21/336 , H01L21/38 , H01L21/425
CPC分类号： H01L29/7816 , H01L21/2253 , H01L21/26513 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/105 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/66795 , H01L29/7835
摘要： The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.
摘要翻译：本公开提供了一种用于制造高压半导体器件的方法。该方法包括在衬底中指定第一，第二和第三区域。第一和第二区域分别是将形成半导体器件的源极和漏极的区域。第三区域分隔第一和第二区域。该方法还包括至少部分地在第三区域上形成开槽的注入掩模层。该方法还包括将掺杂剂注入到第一，第二和第三区域中。开槽植入物掩模层在植入期间保护其下方的第三区域的部分。该方法还包括以使得掺杂剂在第三区域中扩散的方式退火衬底。

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