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1. 发明授权

US08704279B2 Embedded JFETs for high voltage applications 有权
标题翻译：用于高压应用的嵌入式JFET
公开(公告)号：US08704279B2
公开(公告)日：2014-04-22
申请号：US13481462
申请日：2012-05-25
申请人： Jen-Hao Yeh , Chih-Chang Cheng , Ru-Yi Su , Ker Hsiao Huo , Po-Chih Chen , Fu-Chih Yang , Chun Lin Tsai
发明人： Jen-Hao Yeh , Chih-Chang Cheng , Ru-Yi Su , Ker Hsiao Huo , Po-Chih Chen , Fu-Chih Yang , Chun Lin Tsai
IPC分类号： H01L29/80
CPC分类号： H01L29/7832 , H01L29/0692 , H01L29/404 , H01L29/41758 , H01L29/42356 , H01L29/66893 , H01L29/66901 , H01L29/808 , H03K17/223
摘要： A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.
摘要翻译：一种器件包括掩埋阱区和第一导电性的第一HVW区，以及位于第一HVW区上的绝缘区。第一导电类型的漏极区域设置在绝缘区域的第一侧和第一HVW区域的顶表面区域中。与第一导电类型相反的第二导电类型的第一阱区和第二阱区在绝缘区的第二侧上。第一导电类型的第二HVW区域设置在第一和第二阱区域之间，其中第二HVW区域连接到掩埋阱区域。第一导电类型的源极区域位于第二HVW区域的顶表面区域中，其中源极区域，漏极区域和掩埋阱区域形成JFET。

2. 发明申请

US20130313617A1 Embedded JFETs for High Voltage Applications 有权
标题翻译：用于高压应用的嵌入式JFET
公开(公告)号：US20130313617A1
公开(公告)日：2013-11-28
申请号：US13481462
申请日：2012-05-25
申请人： Jen-Hao Yeh , Chih-Chang Cheng , Ru-Yi Su , Ker Hsiao Huo , Po-Chih Chen , Fu-Chih Yang , Chun Lin Tsai
发明人： Jen-Hao Yeh , Chih-Chang Cheng , Ru-Yi Su , Ker Hsiao Huo , Po-Chih Chen , Fu-Chih Yang , Chun Lin Tsai
IPC分类号： H01L29/80
CPC分类号： H01L29/7832 , H01L29/0692 , H01L29/404 , H01L29/41758 , H01L29/42356 , H01L29/66893 , H01L29/66901 , H01L29/808 , H03K17/223
摘要： A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.
摘要翻译：一种器件包括掩埋阱区和第一导电性的第一HVW区，以及位于第一HVW区上的绝缘区。第一导电类型的漏极区域设置在绝缘区域的第一侧和第一HVW区域的顶表面区域中。与第一导电类型相反的第二导电类型的第一阱区和第二阱区在绝缘区的第二侧上。第一导电类型的第二HVW区域设置在第一和第二阱区域之间，其中第二HVW区域连接到掩埋阱区域。第一导电类型的源极区域位于第二HVW区域的顶表面区域中，其中源极区域，漏极区域和掩埋阱区域形成JFET。

3. 发明授权

US08575694B2 Insulated gate bipolar transistor structure having low substrate leakage 有权
公开(公告)号：US08575694B2
公开(公告)日：2013-11-05
申请号：US13372037
申请日：2012-02-13
申请人： Ker Hsiao Huo , Chih-Chang Cheng , Ru-Yi Su , Jen-Hao Yeh , Fu-Chih Yang , Chun Lin Tsai
发明人： Ker Hsiao Huo , Chih-Chang Cheng , Ru-Yi Su , Jen-Hao Yeh , Fu-Chih Yang , Chun Lin Tsai
IPC分类号： H01L29/66 , H01L29/786 , H01L29/02 , H01L23/58 , H01L21/70 , H01L21/336 , H01L21/8238
CPC分类号： H01L29/7394 , H01L21/26533 , H01L21/76243 , H01L21/76283 , H01L29/063 , H01L29/0649 , H01L29/0653 , H01L29/0865 , H01L29/0882 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/42368 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/66325 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7824 , H01L2924/0002 , H01L2924/00
摘要： A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

4. 发明申请

US20120181629A1 HV Interconnection Solution Using Floating Conductors 有权
标题翻译：使用浮动导体的HV互连解决方案
公开(公告)号：US20120181629A1
公开(公告)日：2012-07-19
申请号：US13007220
申请日：2011-01-14
申请人： Ru-Yi Su , Fu-Chih Yang , Chun-Lin Tsai , Ker Hsiao Huo , Chih-Chang Cheng , Ruey-Hsin Liu
发明人： Ru-Yi Su , Fu-Chih Yang , Chun-Lin Tsai , Ker Hsiao Huo , Chih-Chang Cheng , Ruey-Hsin Liu
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L27/088 , H01L29/0692 , H01L29/0696 , H01L29/404 , H01L29/42368 , H01L29/4238 , H01L29/7816 , H01L29/861
摘要： A device includes a first and a second heavily doped region in a semiconductor substrate. An insulation region has at least a portion in the semiconductor substrate, wherein the insulation region is adjacent to the first and the second heavily doped regions. A gate dielectric is formed over the semiconductor substrate and having a portion over a portion of the insulation region. A gate is formed over the gate dielectric. A floating conductor is over and vertically overlapping the insulation region. A metal line includes a portion over and vertically overlapping the floating conductor, wherein the metal line is coupled to, and carries a voltage of, the second heavily doped region.
摘要翻译：一种器件包括半导体衬底中的第一和第二重掺杂区域。绝缘区域在半导体衬底中具有至少一部分，其中绝缘区域与第一和第二重掺杂区域相邻。栅极电介质形成在半导体衬底之上并且具有在绝缘区域的一部分上的部分。栅极形成在栅极电介质上。浮动导体在绝缘区域上方和上方重叠。金属线包括在浮动导体上方并垂直重叠的部分，其中金属线与第二重掺杂区耦合并承载第二重掺杂区的电压。

5. 发明申请

US20120139041A1 HIGH SIDE GATE DRIVER DEVICE 有权
标题翻译：高侧门驱动装置
公开(公告)号：US20120139041A1
公开(公告)日：2012-06-07
申请号：US12959538
申请日：2010-12-03
申请人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Ker Hsiao Huo , Chih-Chang Cheng , Ruey-Hsin Liu
发明人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Ker Hsiao Huo , Chih-Chang Cheng , Ruey-Hsin Liu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L21/76202 , H01L27/0629 , H01L29/0696 , H01L29/1095 , H01L29/42368 , H01L29/861
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region.
摘要翻译：本发明提供一种半导体器件。半导体器件包括：漂移区，其具有形成在衬底中的第一掺杂极性; 掺杂的延伸区域形成在所述漂移区域中并具有与所述第一掺杂极性相反的第二掺杂极性，所述掺杂延伸区域包括横向延伸的部件; 在所述漂移区上形成的电介质结构，所述电介质结构通过所述漂移区的一部分与所述掺杂延伸区分离; 形成在电介质结构的一部分上的栅结构和掺杂延伸区的一部分; 以及具有第二掺杂极性的掺杂隔离区，所述掺杂隔离区至少部分地围绕所述漂移区和所述掺杂延伸区。

6. 发明授权

US08803232B2 High voltage and ultra-high voltage semiconductor devices with increased breakdown voltages 有权
标题翻译：具有增加的击穿电压的高压和超高压半导体器件
公开(公告)号：US08803232B2
公开(公告)日：2014-08-12
申请号：US13186660
申请日：2011-07-20
申请人： Ker Hsiao Huo , Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng
发明人： Ker Hsiao Huo , Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng
IPC分类号： H01L29/66 , H01L29/40 , H01L29/08 , H01L29/78
CPC分类号： H01L29/404 , H01L29/0607 , H01L29/0615 , H01L29/0649 , H01L29/0696 , H01L29/0852 , H01L29/0869 , H01L29/0886 , H01L29/1095 , H01L29/402 , H01L29/41758 , H01L29/4238 , H01L29/49 , H01L29/66674 , H01L29/66681 , H01L29/7801 , H01L29/7816
摘要： A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.
摘要翻译：横向DMOS晶体管设置有源极区，漏极区和导电栅。漏极区域通过在导电栅极下方侵入的场氧化物与导电栅极横向分离。横向DMOS晶体管可以形成为跑道状结构，其中导电栅极包括直线部分和弯曲部分并被源极区域包围。布置在导电栅极和捕获的漏极之间是一层或多层次的层间电介质材料。一组或多组隔离的导体引线形成在电介质层中或介质层上，并且可以设置在多个器件级。隔离导电引线增加了横向DMOS晶体管的击穿电压，特别是在电场拥挤可能会降低击穿电压的弯曲区域中。

7. 发明授权

US08680616B2 High side gate driver device 有权
标题翻译：高边栅驱动器
公开(公告)号：US08680616B2
公开(公告)日：2014-03-25
申请号：US12959538
申请日：2010-12-03
申请人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Ker Hsiao Huo , Chih-Chang Cheng , Ruey-Hsin Liu
发明人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Ker Hsiao Huo , Chih-Chang Cheng , Ruey-Hsin Liu
IPC分类号： H01L21/00
CPC分类号： H01L29/7816 , H01L21/76202 , H01L27/0629 , H01L29/0696 , H01L29/1095 , H01L29/42368 , H01L29/861
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region.
摘要翻译：本发明提供一种半导体器件。半导体器件包括：漂移区，其具有形成在衬底中的第一掺杂极性; 掺杂的延伸区域形成在所述漂移区域中，并且具有与所述第一掺杂极性相反的第二掺杂极性，所述掺杂延伸区域包括横向延伸的部件; 在所述漂移区上形成的电介质结构，所述电介质结构通过所述漂移区的一部分与所述掺杂延伸区分离; 形成在电介质结构的一部分上的栅结构和掺杂延伸区的一部分; 以及具有第二掺杂极性的掺杂隔离区，所述掺杂隔离区至少部分地围绕所述漂移区和所述掺杂延伸区。

8. 发明授权

US08629513B2 HV interconnection solution using floating conductors 有权
标题翻译：使用浮动导体的HV互连解决方案
公开(公告)号：US08629513B2
公开(公告)日：2014-01-14
申请号：US13007220
申请日：2011-01-14
申请人： Ru-Yi Su , Fu-Chih Yang , Chun-Lin Tsai , Ker Hsiao Huo , Chih-Chang Cheng , Ruey-Hsin Liu
发明人： Ru-Yi Su , Fu-Chih Yang , Chun-Lin Tsai , Ker Hsiao Huo , Chih-Chang Cheng , Ruey-Hsin Liu
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L27/088 , H01L29/0692 , H01L29/0696 , H01L29/404 , H01L29/42368 , H01L29/4238 , H01L29/7816 , H01L29/861
摘要： A device includes a first and a second heavily doped region in a semiconductor substrate. An insulation region has at least a portion in the semiconductor substrate, wherein the insulation region is adjacent to the first and the second heavily doped regions. A gate dielectric is formed over the semiconductor substrate and having a portion over a portion of the insulation region. A gate is formed over the gate dielectric. A floating conductor is over and vertically overlapping the insulation region. A metal line includes a portion over and vertically overlapping the floating conductor, wherein the metal line is coupled to, and carries a voltage of, the second heavily doped region.
摘要翻译：一种器件包括半导体衬底中的第一和第二重掺杂区域。绝缘区域在半导体衬底中具有至少一部分，其中绝缘区域与第一和第二重掺杂区域相邻。栅极电介质形成在半导体衬底之上并且具有在绝缘区域的一部分上的部分。栅极形成在栅极电介质上。浮动导体在绝缘区域上方和上方重叠。金属线包括在浮动导体上方并垂直重叠的部分，其中金属线与第二重掺杂区耦合并承载第二重掺杂区的电压。

9. 发明申请

US20110241114A1 HIGH VOLTAGE MOS TRANSISTOR 审中-公开
标题翻译：高压MOS晶体管
公开(公告)号：US20110241114A1
公开(公告)日：2011-10-06
申请号：US12753486
申请日：2010-04-02
申请人： RU-YI SU , Fu-Chih Yang , Chun Lin Tsai , Ker-Hsiao Huo , Chia-Chin Shen , Eric Huang , Chih-Chang Cheng , Ruey-Hsin Liu , Hsiao-Chin Tuan
发明人： RU-YI SU , Fu-Chih Yang , Chun Lin Tsai , Ker-Hsiao Huo , Chia-Chin Shen , Eric Huang , Chih-Chang Cheng , Ruey-Hsin Liu , Hsiao-Chin Tuan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/0634 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7816
摘要： A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS) and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. One portion of the second well surrounds the source and the other portion of the second well extends laterally from the first portion in the first well.
摘要翻译：在本公开中提供了高电压金属氧化物半导体横向扩散装置（HV LDMOS）及其制造方法。该器件包括半导体衬底，形成在衬底上的栅极结构，在栅极结构的任一侧上的衬底中形成的源极和漏极，在衬底中形成的第一掺杂阱和形成在第一衬底中的第二掺杂阱好。第二井的一部分围绕源，第二井的另一部分从第一井的第一部分横向延伸。

10. 发明授权

US08786050B2 High voltage resistor with biased-well 有权
标题翻译：具有偏压井的高压电阻
公开(公告)号：US08786050B2
公开(公告)日：2014-07-22
申请号：US13100714
申请日：2011-05-04
申请人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng , Ruey-Hsin Liu
发明人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng , Ruey-Hsin Liu
IPC分类号： H01L21/02
CPC分类号： H01L28/20 , H01L27/0207 , H01L27/0802
摘要： Provided is a high voltage semiconductor device. The semiconductor device includes a doped well located in a substrate that is oppositely doped. The semiconductor device includes a dielectric structure located on the doped well. A portion of the doped well adjacent the dielectric structure has a higher doping concentration than a remaining portion of the doped well. The semiconductor device includes an elongate polysilicon structure located on the dielectric structure. The elongate polysilicon structure has a length L. The portion of the doped well adjacent the dielectric structure is electrically coupled to a segment of the elongate polysilicon structure that is located away from a midpoint of the elongate polysilicon structure by a predetermined distance that is measured along the elongate polysilicon structure. The predetermined distance is in a range from about 0*L to about 0.1*L.
摘要翻译：提供高压半导体器件。半导体器件包括位于衬底中的相对掺杂的掺杂阱。半导体器件包括位于掺杂阱上的电介质结构。邻近电介质结构的掺杂阱的一部分具有比掺杂阱的剩余部分更高的掺杂浓度。半导体器件包括位于电介质结构上的细长多晶硅结构。细长多晶硅结构具有长度L.与电介质结构相邻的掺杂阱的部分电耦合到细长多晶硅结构的段，其远离细长多晶硅结构的中点远离所测量的预定距离细长多晶硅结构。预定距离在从大约0 * L到大约0.1 * L的范围内。

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