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1. 发明申请

US20080230852A1 Fabrication of FinFETs with multiple fin heights 有权
标题翻译：具有多个翅片高度的FinFET的制造
公开(公告)号：US20080230852A1
公开(公告)日：2008-09-25
申请号：US11714644
申请日：2007-03-06
申请人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fun , Yu-Rung Hsu
发明人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fun , Yu-Rung Hsu
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L21/823431 , H01L27/0886 , H01L29/66795
摘要： A semiconductor structure includes a first semiconductor strip extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the first semiconductor strip has a first height. A first insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the first semiconductor strip, wherein the first insulating region has a first top surface lower than a top surface of the first semiconductor strip. A second semiconductor strip extends from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the second semiconductor strip has a second height greater than the first height. A second insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the second semiconductor strip, wherein the second insulating region has a second top surface lower than the first top surface, and wherein the first and the second insulating regions have substantially same thicknesses.
摘要翻译：半导体结构包括从半导体衬底的顶表面延伸到半导体衬底中的第一半导体条，其中第一半导体条具有第一高度。第一绝缘区域形成在半导体衬底中并围绕第一半导体条的底部，其中第一绝缘区具有比第一半导体条的顶表面低的第一顶表面。第二半导体条从半导体衬底的顶表面延伸到半导体衬底中，其中第二半导体条的第二高度大于第一高度。第二绝缘区域形成在半导体衬底中并围绕第二半导体条的底部，其中第二绝缘区域具有比第一顶表面低的第二顶表面，并且其中第一绝缘区域和第二绝缘区域基本相同厚度

2. 发明授权

US08912602B2 FinFETs and methods for forming the same 有权
标题翻译： FinFET及其形成方法
公开(公告)号：US08912602B2
公开(公告)日：2014-12-16
申请号：US12758426
申请日：2010-04-12
申请人： Yu-Rung Hsu , Chen-Hua Yu , Chen-Nan Yeh
发明人： Yu-Rung Hsu , Chen-Hua Yu , Chen-Nan Yeh
IPC分类号： H01L27/12 , H01L29/78 , H01L29/66
CPC分类号： H01L29/785 , H01L29/66795
摘要： A Fin field effect transistor includes a fin disposed over a substrate. A gate is disposed over a channel portion of the fin. A source region is disposed at a first end of the fin. A drain region is disposed at a second end of the fin. The source region and the drain region are spaced from the substrate by at least one air gap.
摘要翻译： Fin场效应晶体管包括设置在衬底上的鳍。门设置在翅片的通道部分上。源极区域设置在鳍片的第一端。漏极区域设置在鳍片的第二端。源极区域和漏极区域与衬底间隔开至少一个气隙。

3. 发明授权

US07939889B2 Reducing resistance in source and drain regions of FinFETs 有权
标题翻译：降低FinFET源极和漏极区域的电阻
公开(公告)号：US07939889B2
公开(公告)日：2011-05-10
申请号：US11873156
申请日：2007-10-16
申请人： Chen-Hua Yu , Yu-Rung Hsu , Chen-Nan Yeh , Cheng-Hung Chang
发明人： Chen-Hua Yu , Yu-Rung Hsu , Chen-Nan Yeh , Cheng-Hung Chang
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/1033 , H01L27/0886 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer.
摘要翻译：半导体结构包括在基板的顶面上的半导体翅片，其中半导体鳍片包括具有第一宽度的中间部分; 以及连接到中间部分的相对端部的第一和第二端部分，其中第一和第二端部部分至少包括具有大于第一宽度的第二宽度的顶部部分。半导体结构还包括在半导体鳍片的顶表面和中间部分的侧壁上的栅介质层; 以及栅极电介质层上的栅电极。

4. 发明授权

US07843000B2 Semiconductor device having multiple fin heights 有权
标题翻译：具有多个翅片高度的半导体器件
公开(公告)号：US07843000B2
公开(公告)日：2010-11-30
申请号：US12484900
申请日：2009-06-15
申请人： Chen-Hua Yu , Chen-Nan Yeh , Yu-Rung Hsu
发明人： Chen-Hua Yu , Chen-Nan Yeh , Yu-Rung Hsu
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal.
摘要翻译：提供具有多个翅片高度的半导体器件。通过使用多个掩模来在形成在衬底中的沟槽内凹入电介质层来提供多个翅片高度。在另一个实施例中，使用植入模具或电子束光刻来形成光致抗蚀剂材料中的沟槽图案。随后的蚀刻步骤在下面的衬底中形成对应的沟槽。在另一个实施例中，使用多个掩模层来分别蚀刻不同高度的沟槽。可以沿着沟槽的底部形成电介质区域，以通过执行离子注入和随后的退火来隔离散热片。

5. 发明授权

US07560785B2 Semiconductor device having multiple fin heights 有权
标题翻译：具有多个翅片高度的半导体器件
公开(公告)号：US07560785B2
公开(公告)日：2009-07-14
申请号：US11741580
申请日：2007-04-27
申请人： Chen-Hua Yu , Chen-Nan Yeh , Yu-Rung Hsu
发明人： Chen-Hua Yu , Chen-Nan Yeh , Yu-Rung Hsu
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal.
摘要翻译：提供具有多个翅片高度的半导体器件。通过使用多个掩模来在形成在衬底中的沟槽内凹入电介质层来提供多个翅片高度。在另一个实施例中，使用植入模具或电子束光刻来形成光致抗蚀剂材料中的沟槽图案。随后的蚀刻步骤在下面的衬底中形成对应的沟槽。在另一个实施例中，使用多个掩模层来分别蚀刻不同高度的沟槽。可以沿着沟槽的底部形成电介质区域，以通过执行离子注入和随后的退火来隔离散热片。

6. 发明申请

US20090095980A1 Reducing Resistance in Source and Drain Regions of FinFETs 有权
标题翻译：降低FinFET源极和漏极区域的电阻
公开(公告)号：US20090095980A1
公开(公告)日：2009-04-16
申请号：US11873156
申请日：2007-10-16
申请人： Chen-Hua Yu , Yu-Rung Hsu , Chen-Nan Yeh , Cheng-Hung Chang
发明人： Chen-Hua Yu , Yu-Rung Hsu , Chen-Nan Yeh , Cheng-Hung Chang
IPC分类号： H01L29/778 , H01L29/786
CPC分类号： H01L29/1033 , H01L27/0886 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer.
摘要翻译：半导体结构包括在基板的顶面上的半导体翅片，其中半导体鳍片包括具有第一宽度的中间部分; 以及连接到中间部分的相对端部的第一和第二端部分，其中第一和第二端部部分至少包括具有大于第一宽度的第二宽度的顶部部分。半导体结构还包括在半导体鳍片的顶表面和中间部分的侧壁上的栅介质层; 以及栅极电介质层上的栅电极。

7. 发明申请

US20090035909A1 METHOD OF FABRICATION OF A FINFET ELEMENT 有权
标题翻译： FINFET元件的制造方法
公开(公告)号：US20090035909A1
公开(公告)日：2009-02-05
申请号：US11831098
申请日：2007-07-31
申请人： Cheng-Hung Chang , Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Yu-Rung Hsu , Ding-Yuan Chen
发明人： Cheng-Hung Chang , Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Yu-Rung Hsu , Ding-Yuan Chen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823828 , H01L21/823807 , H01L21/823821 , H01L21/823857 , H01L29/66795 , H01L29/785
摘要： The present disclosure provides a method of fabricating a FinFET element including providing a substrate including a first fin and a second fin. A first layer is formed on the first fin. The first layer comprises a dopant of a first type. A dopant of a second type is provided to the second fin. High temperature processing of the substrate is performed on the substrate including the formed first layer and the dopant of the second type.
摘要翻译：本公开提供了一种制造FinFET元件的方法，包括提供包括第一鳍片和第二鳍片的衬底。在第一散热片上形成第一层。第一层包括第一类型的掺杂剂。第二类型的掺杂剂被提供到第二鳍。在包括所形成的第一层和第二类型的掺杂剂的衬底上进行衬底的高温处理。

8. 发明授权

US11038056B2 System and method for source/drain contact processing 有权
公开(公告)号：US11038056B2
公开(公告)日：2021-06-15
申请号：US13371169
申请日：2012-02-10
申请人： Chen-Hua Yu , Cheng-Hung Chang , Chen-Nan Yeh , Yu-Rung Hsu
发明人： Chen-Hua Yu , Cheng-Hung Chang , Chen-Nan Yeh , Yu-Rung Hsu
IPC分类号： H01L29/76 , H01L29/78 , H01L29/417 , H01L29/66 , H01L29/20
摘要： System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.

9. 发明申请

US20120025313A1 Germanium FinFETs Having Dielectric Punch-Through Stoppers 有权
标题翻译：具有介质穿孔塞的锗FinFET
公开(公告)号：US20120025313A1
公开(公告)日：2012-02-02
申请号：US13272994
申请日：2011-10-13
申请人： Cheng-Hung Chang , Yu-Rung Hsu , Chen-Yi Lee , Shih-Ting Hung , Chen-Nan Yeh , Chen-Hua Yu
发明人： Cheng-Hung Chang , Yu-Rung Hsu , Chen-Yi Lee , Shih-Ting Hung , Chen-Nan Yeh , Chen-Hua Yu
IPC分类号： H01L27/12 , H01L29/02
CPC分类号： H01L29/66795 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02617 , H01L29/1054 , H01L29/7851
摘要： A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fin. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.
摘要翻译：形成半导体结构的方法包括提供复合衬底，该复合衬底包括在本体硅衬底上并邻接体硅衬底的体硅衬底和硅锗（SiGe）层。对SiGe层进行第一次冷凝以形成冷凝的SiGe层，使得冷凝的SiGe层具有基本均匀的锗浓度。蚀刻冷凝的SiGe层和体硅衬底的顶部以在硅片上形成包括硅翅片和冷凝的SiGe鳍的复合翅片。该方法还包括氧化硅片的一部分; 并对冷凝的SiGe翅片进行第二冷凝。

10. 发明授权

US08048723B2 Germanium FinFETs having dielectric punch-through stoppers 有权
标题翻译：锗FinFET具有绝缘穿孔塞
公开(公告)号：US08048723B2
公开(公告)日：2011-11-01
申请号：US12329279
申请日：2008-12-05
申请人： Cheng-Hung Chang , Yu-Rung Hsu , Chen-Yi Lee , Shih-Ting Hung , Chen-Nan Yeh , Chen-Hua Yu
发明人： Cheng-Hung Chang , Yu-Rung Hsu , Chen-Yi Lee , Shih-Ting Hung , Chen-Nan Yeh , Chen-Hua Yu
IPC分类号： H01L21/332
CPC分类号： H01L29/66795 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02617 , H01L29/1054 , H01L29/7851
摘要： A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.
摘要翻译：形成半导体结构的方法包括提供复合衬底，该复合衬底包括在本体硅衬底上并邻接体硅衬底的体硅衬底和硅锗（SiGe）层。对SiGe层进行第一次冷凝以形成冷凝的SiGe层，使得冷凝的SiGe层具有基本均匀的锗浓度。蚀刻冷凝的SiGe层和体硅衬底的顶部以形成包括硅片和在硅微细上的冷凝的SiGe鳍的复合翅片。该方法还包括氧化硅片的一部分; 并对冷凝的SiGe翅片进行第二冷凝。

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