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1. 发明授权

US5668065A Process for simultaneous formation of silicide-based self-aligned contacts and local interconnects 失效
标题翻译：用于同时形成基于硅化物的自对准触点和局部互连的工艺
公开(公告)号：US5668065A
公开(公告)日：1997-09-16
申请号：US690972
申请日：1996-08-01
申请人： Chen-Hsi Lin
发明人： Chen-Hsi Lin
IPC分类号： H01L21/60 , H01L21/768 , H01L21/283 , H01L21/335
CPC分类号： H01L21/76897 , H01L21/76889 , H01L21/76895
摘要： A process for simultaneously forming a self-aligned contact, a local interconnect and a self-aligned silicide in a semiconductor device. An oxide layer is deposited over a gate structure, a source region and a drain region formed on a substrate of the semiconductor device. The gate structure may be a multi-layer structure including a polysilicon gate, a silicon nitride layer and a tungsten silicide layer. The oxide layer deposited over the gate, source and drain is etched to define portions of the oxide layer which will form contact areas of a self-aligned contact and a local interconnect of the semiconductor device. An amorphous silicon layer is then deposited over the etched oxide layer to a thickness selected such that substantially the entire thickness of remaining portions of the amorphous silicon layer will be consumed during a subsequent silicidation reaction. The amorphous silicon layer is etched to remove portions of the amorphous silicon layer which will not be used to form a portion of the self-aligned contact and local interconnect, as well as remaining non-contact area portions of the underlying oxide layer. A metal layer is deposited over the etched amorphous silicon layer, and an annealing process is applied such that the etched amorphous silicon layer and the deposited metal layer react to provide a silicide layer which forms a portion of the self-aligned contact and the local interconnect. The annealing process also causes the deposited metal layer to react with exposed source and/or drain regions to thereby form a self-aligned silicide.
摘要翻译：一种在半导体器件中同时形成自对准接触，局部互连和自对准硅化物的方法。氧化物层沉积在形成在半导体器件的衬底上的栅极结构，源极区和漏极区上。栅极结构可以是包括多晶硅栅极，氮化硅层和硅化钨层的多层结构。蚀刻沉积在栅极，源极和漏极上的氧化物层以限定氧化物层的部分，其将形成半导体器件的自对准接触和局部互连的接触区域。然后将非晶硅层沉积在蚀刻的氧化物层上，以选择厚度，使得在随后的硅化反应期间，非晶硅层的剩余部分的整个厚度将被消耗。蚀刻非晶硅层以去除不用于形成自对准接触和局部互连的一部分的部分，以及下面的氧化物层的剩余非接触区域部分。在蚀刻的非晶硅层上沉积金属层，并且施加退火处理，使得蚀刻的非晶硅层和沉积的金属层反应以提供形成自对准接触的一部分的硅化物层和局部互连。退火工艺还使沉积的金属层与暴露的源极和/或漏极区域反应，从而形成自对准的硅化物。

2. 发明授权

US5158900A Method of separately fabricating a base/emitter structure of a BiCMOS device 失效
标题翻译：分别制造BiCMOS器件的基极/发射极结构的方法
公开(公告)号：US5158900A
公开(公告)日：1992-10-27
申请号：US779448
申请日：1991-10-18
申请人： Chi-Kwan Lau , Donald L. Packwood , Chen-Hsi Lin , Ashor Kapoor
发明人： Chi-Kwan Lau , Donald L. Packwood , Chen-Hsi Lin , Ashor Kapoor
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L21/8249
摘要： A method of fabricating a BiCMOS device in which PMOS and NMOS transistors are formed prior to a base/emitter structure of a bipolar transistor. In forming the base/emitter structure, a blanket implant of a first impurity is introduced into a base region of a semiconductor substrate. An insulating layer is deposited and then patterned to expose a portion of the base region at an emitter window. A polysilicon layer is deposited on the insulating layer and into the emitter window. The polysilicon layer is patterned to provide the desired configuration at the emitter window, whereafter the remaining polysilicon acts as a mask for etching of the insulating layer. Thus, etching of the insulating layer is performed in a self-aligning manner. Self-alignment is also utilized in providing a base-link region and in providing a silicide layer.
摘要翻译：一种制造BiCMOS器件的方法，其中在双极晶体管的基极/发射极结构之前形成PMOS和NMOS晶体管。在形成基极/发射极结构时，将第一杂质的覆盖注入引入到半导体衬底的基极区域中。沉积绝缘层，然后将其图案化以在发射器窗口处暴露基部区域的一部分。多晶硅层沉积在绝缘层上并进入发射极窗口。图案化多晶硅层以在发射极窗口处提供期望的配置，此后剩余的多晶硅用作蚀刻绝缘层的掩模。因此，以自对准的方式进行绝缘层的蚀刻。自对准也用于提供基极连接区域和提供硅化物层。

3. 发明授权

US5108542A Selective etching method for tungsten and tungsten alloys 失效
标题翻译：钨和钨合金的选择性蚀刻方法
公开(公告)号：US5108542A
公开(公告)日：1992-04-28
申请号：US572188
申请日：1990-08-23
申请人： Chen-Hsi Lin
发明人： Chen-Hsi Lin
IPC分类号： C23F4/00 , H01L21/302 , H01L21/3065 , H01L21/3213
CPC分类号： H01L21/32136 , C23F4/00
摘要： A method of plasma etching tungsten containing films such as is found in semiconductor interconnects. The etch method is conducted under reactive ion etch conditions in a plasma etch reactor using a gas mixture of CF.sub.4 and O.sub.2. The O.sub.2 preferably makes up 20% to 60% of the gas mixture by volume. The etch method is highly selective to titanium disilicide, titanium nitride and silicon dioxide.
摘要翻译：在半导体互连中发现等离子体蚀刻含钨膜的方法。蚀刻方法在等离子体蚀刻反应器中使用CF 4和O 2的气体混合物在反应离子蚀刻条件下进行。氧气优选占体积气体混合物的20％至60％。蚀刻方法对二硅化钛，氮化钛和二氧化硅具有高选择性。

4. 发明授权

US6026028A Hot carrier injection programming and negative gate voltage channel erase flash EEPROM structure 失效
标题翻译：热载波注入编程和负栅极电压通道擦除闪存EEPROM结构
公开(公告)号：US6026028A
公开(公告)日：2000-02-15
申请号：US123305
申请日：1998-07-28
申请人： Chen-Hsi Lin , Chih-Ming Chen , Ling-Sung Wang , Horng-Ming Lee , Ko-Hsing Chang
发明人： Chen-Hsi Lin , Chih-Ming Chen , Ling-Sung Wang , Horng-Ming Lee , Ko-Hsing Chang
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： H01L29/7885
摘要： A flash electrical erasable programmable read only memory structure that utilizes hot carrier injection for programming and negative gate voltage to carry out channel erase operations. Characteristic of the memory structure includes a triple well structure having a P-well and an N-well located within a P-type substrate, wherein the N-well isolated the P-well from the P-type substrate. Therefore, an independently isolated triple well structure is established during memory erase operation.
摘要翻译：闪存电可擦除可编程只读存储器结构，其利用热载流子注入用于编程和负栅极电压来执行通道擦除操作。存储器结构的特征包括具有P阱和位于P型衬底内的N阱的三阱结构，其中N阱从P型衬底隔离P阱。因此，在存储器擦除操作期间建立独立隔离的三重阱结构。

5. 发明授权

US5476800A Method for formation of a buried layer for a semiconductor device 失效
标题翻译：用于形成半导体器件的掩埋层的方法
公开(公告)号：US5476800A
公开(公告)日：1995-12-19
申请号：US189353
申请日：1994-01-31
申请人： Gregory N. Burton , Chen-Hsi Lin , Chi-Kwan Lau
发明人： Gregory N. Burton , Chen-Hsi Lin , Chi-Kwan Lau
IPC分类号： H01L21/74 , H01L21/265
CPC分类号： H01L21/74
摘要： The present invention provides a buried layer fabrication sequence suitable for bipolar and BiCMOS applications. The buried layer fabrication sequence for forming a buried layer having a first conductivity type includes the steps of: forming a first dielectric layer on a semiconductor substrate, the semiconductor substrate having a second conductivity type; forming a first mask layer having openings on top of the first dielectric layer, wherein the openings in the first mask layer are positioned over the regions where the first buried layer is formed; exposing the semiconductor substrate in the regions where openings in the first mask layer are formed; forming a second dielectric layer; removing the second dielectric layer; and forming a semiconductor layer.
摘要翻译：本发明提供了适用于双极和BiCMOS应用的掩埋层制造序列。用于形成具有第一导电类型的掩埋层的掩埋层制造顺序包括以下步骤：在半导体衬底上形成第一电介质层，所述半导体衬底具有第二导电类型; 在所述第一介电层的顶部上形成具有开口的第一掩模层，其中所述第一掩模层中的所述开口位于形成有所述第一掩埋层的区域上; 在形成第一掩模层中的开口的区域中暴露半导体衬底; 形成第二电介质层; 去除所述第二电介质层; 并形成半导体层。

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