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1. 发明申请

US20050144413A1 Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches 有权
标题翻译：利用非均匀分布的DRAM配置并检测范围内的存储器地址匹配的方法和装置
公开(公告)号：US20050144413A1
公开(公告)日：2005-06-30
申请号：US10751263
申请日：2003-12-30
申请人： Chen-Chi Kuo , Sridhar Lakshmanamurthy , Rohit Natarajan , Kin-Yip Liu , Prashant Chandra , James Guilford
发明人： Chen-Chi Kuo , Sridhar Lakshmanamurthy , Rohit Natarajan , Kin-Yip Liu , Prashant Chandra , James Guilford
IPC分类号： G06F12/08 , G06F13/42
CPC分类号： G06F13/4243
摘要： Methods, software and systems to determine channel ownership and physical block location within the channel in non-uniformly distributed DRAM configurations and also to detect in-range memory address matches are presented. A first method, which may also be implemented in software and/or hardware, allocates memory non-uniformly between a number of memory channels, determines a selected memory channel from the memory channels for a program address, and maps the program address to a physical address within the selected memory channel. A second method, which may also be implemented in software and/or hardware, designates a range of memory to perform address matching, monitors memory accesses and when a memory access occurs with the specified range, perform a particular function.
摘要翻译：给出了在非均匀分布的DRAM配置中确定通道中的通道所有权和物理块位置的方法，软件和系统，以及检测范围内的存储器地址匹配。还可以在软件和/或硬件中实现的第一种方法在多个存储器通道之间非均匀地分配存储器，从存储器通道确定用于程序地址的所选择的存储器通道，并将程序地址映射到物理所选内存通道内的地址。也可以在软件和/或硬件中实现的第二种方法指定一系列存储器来执行地址匹配，监视存储器访问以及当以指定范围发生存储器访问时，执行特定功能。

2. 发明申请

US20060150165A1 Virtual microengine systems and methods 审中-公开
标题翻译：虚拟微型发动机系统和方法
公开(公告)号：US20060150165A1
公开(公告)日：2006-07-06
申请号：US11027785
申请日：2004-12-30
申请人： Donald Hooper , Prashant Chandra , James Guilford , Mark Rosenbluth
发明人： Donald Hooper , Prashant Chandra , James Guilford , Mark Rosenbluth
IPC分类号： G06F9/45
CPC分类号： G06F9/455
摘要： Systems and methods are disclosed for supporting virtual microengines in a multithreaded processor, such as a microengine running on a network processor. In one embodiment code is written for execution by a plurality of virtual microengines. The code is than compiled and linked for execution on a physical microengine, at which time the physical microengine's threads are assigned to thread groups corresponding to the virtual microengines. Internal next neighbor rings are allocated within the physical microengine to facilitate communication between the thread groups. The code can then be loaded onto the physical microengine and executed, with each thread group executing the code written for its corresponding virtual microengine.
摘要翻译：公开了用于在多线程处理器中支持虚拟微引擎的系统和方法，诸如在网络处理器上运行的微型引擎。在一个实施例中，代码被写入以由多个虚拟微引擎执行。代码被编译和链接以在物理微引擎上执行，此时物理微引擎的线程被分配给对应于虚拟微引擎的线程组。内部下一个邻居环在物理微引擎内分配，以促进线程组之间的通信。然后可以将代码加载到物理微引擎上并执行，每个线程组执行为其相应的虚拟微引擎编写的代码。

3. 发明申请

US20050210457A1 Debug system having assembler correcting register allocation errors 失效
标题翻译：具有汇编器校正寄存器分配错误的调试系统
公开(公告)号：US20050210457A1
公开(公告)日：2005-09-22
申请号：US10807218
申请日：2004-03-22
申请人： James Guilford
发明人： James Guilford
IPC分类号： G06F9/45
CPC分类号： G06F11/3624
摘要： An assembler, which can be provided as part of a debugger and/or development system, avoids register allocation errors, such as register bank conflicts and/or insufficient physical registers, automatically.
摘要翻译：可以作为调试器和/或开发系统的一部分提供的汇编器自动避免寄存器分配错误，例如寄存器组冲突和/或不足的物理寄存器。

4. 发明申请

US20050278707A1 Method and system providing virtual resource usage information 审中-公开
标题翻译：提供虚拟资源使用信息的方法和系统
公开(公告)号：US20050278707A1
公开(公告)日：2005-12-15
申请号：US10864666
申请日：2004-06-09
申请人： James Guilford
发明人： James Guilford
IPC分类号： G06F9/44
CPC分类号： G06F11/3476 , G06F11/3495
摘要： A method and system to provide virtual resource usage information for assembler programs. In one embodiment, a graphical user interface displays virtual resource usage for portions of an assembler program.
摘要翻译：一种为汇编程序提供虚拟资源使用信息的方法和系统。在一个实施例中，图形用户界面显示汇编程序的部分的虚拟资源使用。

5. 发明授权

US09292283B2 Method for fast large-integer arithmetic on IA processors 有权
标题翻译：在IA处理器上进行快速大整数运算的方法
公开(公告)号：US09292283B2
公开(公告)日：2016-03-22
申请号：US13707105
申请日：2012-12-06
申请人： Erdinc Ozturk , Vinodh Gopal , James Guilford
发明人： Erdinc Ozturk , Vinodh Gopal , James Guilford
IPC分类号： G06F7/523 , G06F9/30 , G06F7/52
CPC分类号： G06F9/3001 , G06F7/52 , G06F7/523 , G06F7/544 , G06F9/30036 , G06F2207/5523
摘要： Methods, systems, and apparatuses are disclosed for implementing fast large-integer arithmetic within an integrated circuit, such as on IA (Intel Architecture) processors, in which such means include receiving a 512-bit value for squaring, the 512-bit value having eight sub-elements each of 64-bits and performing a 512-bit squaring algorithm by: (i) multiplying every one of the eight sub-elements by itself to yield a square of each of the eight sub-elements, the eight squared sub-elements collectively identified as T1, (ii) multiplying every one of the eight sub-elements by the other remaining seven of the eight sub-elements to yield an asymmetric intermediate result having seven diagonals therein, wherein each of the seven diagonals are of a different length, (iii) reorganizing the asymmetric intermediate result having the seven diagonals therein into a symmetric intermediate result having four diagonals each of 7×1 sub-elements of the 64-bits in length arranged across a plurality of columns, (iv) adding all sub-elements within their respective columns, the added sub-elements collectively identified as T2, and (v) yielding a final 512-bit squared result of the 512-bit value by adding the value of T2 twice with the value of T1 once. Other related embodiments are disclosed.
摘要翻译：公开了用于在诸如IA（Intel Architecture）处理器之类的集成电路内实现快速大整数运算的方法，系统和装置，其中这种装置包括接收512位的平方值，512位值具有八个子元素，每个64位，并通过以下方式执行512位平方算法：（i）将八个子元素中的每一个本身相乘以产生八个子元素中的每一个的平方，八个子元素 - 集体标识为T1的元件，（ii）将八个子元素中的每一个乘以八个子元素中的其余七个子元素以产生其中具有七个对角线的不对称中间结果，其中七个对角线中的每一个为（iii）将其中具有七个对角线的非对称中间结果重新组合成具有四个对角线的对称中间结果，每个对角线的长度为64位的7×1个子元素跨越多个列，（iv）将其所有列中的所有子元素加入集体标识为T2的所添加的子元素，以及（v）通过将T2值增加两次来产生512位值的最终512位平方结果其T1值一次。公开了其他相关实施例。

6. 发明申请

US20050273776A1 Assembler supporting pseudo registers to resolve return address ambiguity 审中-公开
标题翻译：汇编器支持伪寄存器来解决返回地址模糊
公开(公告)号：US20050273776A1
公开(公告)日：2005-12-08
申请号：US10863300
申请日：2004-06-08
申请人： James Guilford
发明人： James Guilford
IPC分类号： G06F9/42 , G06F9/45
CPC分类号： G06F11/3624 , G06F9/4486
摘要： An assembler, which can form part of a development/debug system, supports pseudo instructions to enable the assembler to resolve return address ambiguities.
摘要翻译：汇编器可以构成开发/调试系统的一部分，支持伪指令，使汇编程序能够解决返回地址模糊。

7. 发明申请

US20050251795A1 Method, system, and program for optimizing code 审中-公开
标题翻译：用于优化代码的方法，系统和程序
公开(公告)号：US20050251795A1
公开(公告)日：2005-11-10
申请号：US10805106
申请日：2004-03-19
申请人： Mariano Fernandez , James Guilford
发明人： Mariano Fernandez , James Guilford
IPC分类号： G06F7/38
CPC分类号： G06F8/4441
摘要： Provided are a method, system, and program for optimizing code. A program is accessed comprising a plurality of instructions including at least one no operation (NOP) instruction. At least one NOP instruction in the program that is not needed to provide a processing delay to ensure data is available to at least one dependent instruction accessing the data is removed.
摘要翻译：提供了一种用于优化代码的方法，系统和程序。访问包括至少一个无操作（NOP）指令的多个指令的程序。程序中至少有一个NOP指令不需要提供处理延迟来确保数据可用于访问数据的至少一个依赖指令。

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