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1. 发明授权

US07239254B1 Programmable multi-cycle signaling in integrated circuits 失效
标题翻译：集成电路中的可编程多周期信号
公开(公告)号：US07239254B1
公开(公告)日：2007-07-03
申请号：US11394510
申请日：2006-03-31
申请人： Suryaprasad Kareenahalli , Zohar Bogin , Chee Hak Teh
发明人： Suryaprasad Kareenahalli , Zohar Bogin , Chee Hak Teh
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03K5/135 , H03K5/15066
摘要： A programmable multi-cycle signaling scheme provides synchronous communications over relatively large distances. An input digital data stream is de-multiplexed onto multiple conductors. The digital data stream is recreated at the far end of the conductors.
摘要翻译：可编程多周期信令方案提供了相对较大距离的同步通信。输入数字数据流被解复用到多个导体上。在导体的远端重建数字数据流。

2. 发明授权

US07587547B2 Dynamic update adaptive idle timer 失效
标题翻译：动态更新自适应空闲定时器
公开(公告)号：US07587547B2
公开(公告)日：2009-09-08
申请号：US11394461
申请日：2006-03-30
申请人： Chee Hak Teh , Suryaprasad Kareenahalli , Zohar Bogin
发明人： Chee Hak Teh , Suryaprasad Kareenahalli , Zohar Bogin
IPC分类号： G06F12/00
CPC分类号： G06F13/161 , G06F12/0215
摘要： The invention describes a technology for closing DRAM pages, wherein the invention allows for dynamically changing code streams by tracking the previous decisions made on page closes and adjusts dynamically during DRAM operation to compensate for bad page close decisions made.
摘要翻译：本发明描述了一种用于关闭DRAM页面的技术，其中本发明允许通过跟踪在页面关闭时做出的先前决定来动态地改变代码流，并且在DRAM操作期间动态调整以补偿所做出的错误页面关闭决定。

3. 发明授权

US07409516B2 Pending request scoreboard for out-of-order memory scheduler 失效
标题翻译：针对无序内存调度程序的待处理请求记分板
公开(公告)号：US07409516B2
公开(公告)日：2008-08-05
申请号：US11394462
申请日：2006-03-30
申请人： Chee Hak Teh , Suryaprasad Kareenahalli , Zohar Bogin
发明人： Chee Hak Teh , Suryaprasad Kareenahalli , Zohar Bogin
IPC分类号： G06F12/00
CPC分类号： G06F13/1668 , G06F12/0215
摘要： Embodiments of a memory scoreboard are presented herein. The memory scoreboard tracks memory requests for each rank and bank of memory being addressed. When there are no pending requests, the scoreboard provides an indication to an idle timer that begins a count down to close a current page of the memory. The idle timer can be configured dynamically to close memory pages and to address dynamically-changing code streams by tracking previous decisions made on page closes.
摘要翻译：记忆记分板的实施例在本文中给出。记忆记分板跟踪正在寻址的每个等级和存储体的存储器请求。当没有未决请求时，记分板向空闲计时器提供指示，该空闲计时器开始向下计数以关闭存储器的当前页面。可以动态配置空闲计时器以关闭内存页面，并通过跟踪页面关闭时做出的以前决定来解决动态变化的代码流。

4. 发明申请

US20080144405A1 Data strobe timing compensation 审中-公开
标题翻译：数据选通定时补偿
公开(公告)号：US20080144405A1
公开(公告)日：2008-06-19
申请号：US11642318
申请日：2006-12-18
申请人： Chee Hak Teh , Suryaprasad Kareenahalli , Zohar Bogin
发明人： Chee Hak Teh , Suryaprasad Kareenahalli , Zohar Bogin
IPC分类号： G11C7/10
CPC分类号： G06F13/4239
摘要： A method, apparatus, and system are disclosed. In one embodiment, the method receiving data from a memory on a first interconnect of at least one interconnect, receiving a source-synchronous data strobe from the memory, creating at least a nominal, an early, and a delayed compensated data strobe from the received data strobe, latching the received data with the nominal, early, or delayed compensated data strobe, outputting the latched data onto one or more of the at least one interconnect.
摘要翻译：公开了一种方法，装置和系统。在一个实施例中，该方法从至少一个互连的第一互连上的存储器接收数据，从存储器接收源同步数据选通脉冲，从接收到的数据选通产生至少一个标称，早期和延迟补偿的数据选通数据选通，使用标称，早期或延迟补偿的数据选通来锁存所接收的数据，将锁存的数据输出到所述至少一个互连中的一个或多个上。

5. 发明授权

US08650629B2 Interface logic for a multi-core system-on-a-chip (SoC) 失效
标题翻译：多核系统芯片（SoC）的接口逻辑
公开(公告)号：US08650629B2
公开(公告)日：2014-02-11
申请号：US12639258
申请日：2009-12-16
申请人： Ramana Rachakonda , Lance E. Hacking , Mahesh K. Reddy , Lori R. Borger , Chee Hak Teh , Pawitter P. Bhatia , John P. Lee
发明人： Ramana Rachakonda , Lance E. Hacking , Mahesh K. Reddy , Lori R. Borger , Chee Hak Teh , Pawitter P. Bhatia , John P. Lee
IPC分类号： G06F21/22
CPC分类号： G06F13/40 , G01R31/318572 , G06F15/7807 , G06F15/7842 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有第一和第二核心的系统级芯片（SoC），耦合到核心的接口逻辑，耦合到接口逻辑的芯片组逻辑以及耦合在芯片组逻辑之间的虚拟防火墙逻辑和第二核心。接口逻辑可以包括防火墙逻辑，总线逻辑和测试逻辑，并且芯片组逻辑可以包括存储器控制器以提供与耦合到SoC的存储器的通信。在一些系统实现中，无论是在测试操作还是功能操作期间，在正常操作期间可以禁用第二个内核以提供单个核心SoC，从而在许多不同实现中使SoC的灵活性更高。描述和要求保护其他实施例。

6. 发明申请

US20130007332A1 CONTROLLABLE TRANSACTION SYNCHRONIZATION FOR PERIPHERAL DEVICES 有权
标题翻译：外围设备的可控交易同步
公开(公告)号：US20130007332A1
公开(公告)日：2013-01-03
申请号：US13174436
申请日：2011-06-30
申请人： Chee Hak Teh , Chai Huat Gan , Poh Thiam Teoh , Mary Siaw See Yeoh , Su Wei Lim
发明人： Chee Hak Teh , Chai Huat Gan , Poh Thiam Teoh , Mary Siaw See Yeoh , Su Wei Lim
IPC分类号： G06F13/20
CPC分类号： G06F13/385 , G06F13/4022
摘要： Embodiments of the invention describe a host system capable of associating a PCIe device and another separate device to the same device identifier (e.g., device number). A cycle routing module or logic will identify an I/O transaction involving the device identifier, and route the transaction to one or both of the devices (or, in some instances, identify the I/O transaction as a configuration transaction, and simply update the cycle routing module/logic only). In one embodiment of the invention, a root port of the host system is configured to operate as the above described cycle router.Embodiments of the invention allow for devices to be “merged” into a single device for the host OS. For example, a peripheral devices coupled to the host system via a PCIe link may be “merged” with a peripheral devices coupled to the host system via another PCIe link or a SATA link.
摘要翻译：本发明的实施例描述了能够将PCIe设备和另一单独的设备关联到相同设备标识符（例如，设备号码）的主机系统。周期路由模块或逻辑将识别涉及设备标识符的I / O事务，并将事务路由到一个或两个设备（或者在某些情况下，将I / O事务标识为配置事务，并且简单地更新循环路由模块/逻辑）。在本发明的一个实施例中，主机系统的根端口被配置为作为上述循环路由器进行操作。本发明的实施例允许将设备合并到用于主机OS的单个设备中。例如，经由PCIe链路耦合到主机系统的外围设备可以与经由另一PCIe链路或SATA链路耦合到主机系统的外围设备合并。

7. 发明申请

US20110145909A1 Interface Logic For A Multi-Core System-On-A-Chip (SoC) 失效
标题翻译：多核系统芯片（SoC）的接口逻辑
公开(公告)号：US20110145909A1
公开(公告)日：2011-06-16
申请号：US12639258
申请日：2009-12-16
申请人： Ramana Rachakonda , Lance E. Hacking , Mahesh K. Reddy , Lori R. Borger , Chee Hak Teh , Pawitter P. Bhatia , John P. Lee
发明人： Ramana Rachakonda , Lance E. Hacking , Mahesh K. Reddy , Lori R. Borger , Chee Hak Teh , Pawitter P. Bhatia , John P. Lee
IPC分类号： G06F21/22
CPC分类号： G06F13/40 , G01R31/318572 , G06F15/7807 , G06F15/7842 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有第一和第二核心的系统级芯片（SoC），耦合到核心的接口逻辑，耦合到接口逻辑的芯片组逻辑以及耦合在芯片组逻辑之间的虚拟防火墙逻辑和第二核心。接口逻辑可以包括防火墙逻辑，总线逻辑和测试逻辑，并且芯片组逻辑可以包括存储器控制器以提供与耦合到SoC的存储器的通信。在一些系统实现中，无论是在测试操作还是功能操作期间，在正常操作期间可以禁用第二个内核以提供单个核心SoC，从而在许多不同实现中使SoC的灵活性更高。描述和要求保护其他实施例。

8. 发明授权

US08140781B2 Multi-level page-walk apparatus for out-of-order memory controllers supporting virtualization technology 有权
标题翻译：用于支持虚拟化技术的无序内存控制器的多级页面移动设备
公开(公告)号：US08140781B2
公开(公告)日：2012-03-20
申请号：US11967997
申请日：2007-12-31
申请人： Chee Hak Teh , Arthur D Hunter
发明人： Chee Hak Teh , Arthur D Hunter
IPC分类号： G09G5/39 , G06F13/00 , G06F12/06 , G06F12/00
CPC分类号： G06F12/1081 , G06F12/10
摘要： The invention relates generally to computer memory access. Embodiments of the invention provide a multi-level page-walk apparatus and method that enable I/O devices to execute multi-level page-walks with an out-of-order memory controller. In embodiments of the invention, the multi-level page-walk apparatus includes a demotion-based priority grant arbiter, a page-walk tracking queue, a page-walk completion queue, and a command packetizer.
摘要翻译：本发明一般涉及计算机存储器访问。本发明的实施例提供了一种使得I / O设备能够用无序存储器控制器执行多级页面移动的多级页面移动设备和方法。在本发明的实施例中，多级页面移动装置包括基于降级的优先授权仲裁器，寻呼步行跟踪队列，页面遍历完成队列和命令打包器。

9. 发明授权

US07685346B2 Demotion-based arbitration 失效
标题翻译：基于降级的仲裁
公开(公告)号：US07685346B2
公开(公告)日：2010-03-23
申请号：US11821873
申请日：2007-06-26
申请人： Chee Hak Teh , Arthur Hunter
发明人： Chee Hak Teh , Arthur Hunter
IPC分类号： G06F13/14
CPC分类号： H04L12/56
摘要： In one embodiment, the present invention includes a method for arbitrating requests from multiple agents based on an arbitration list to select an agent to receive an arbitration grant, determining whether the selected agent is associated with a grant counter that is at a value of zero, and if so dynamically reordering the arbitration list so that the selected agent is demoted to the lowest portion of the arbitration list. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于根据仲裁列表仲裁来自多个代理的请求的方法，以选择代理接收仲裁授权，确定所选择的代理是否与零值的授权计数器相关联，并且如果是这样动态地重新排序仲裁列表，使得所选择的代理被降级到仲裁列表的最低部分。描述和要求保护其他实施例。

10. 发明申请

US20190326210A1 Fabric Die to Fabric Die Interconnect for Modularized Integrated Circuit Devices 审中-公开
公开(公告)号：US20190326210A1
公开(公告)日：2019-10-24
申请号：US16456647
申请日：2019-06-28
申请人： Chee Hak Teh , Chee Seng Leong , Lai Guan Tang , Han Wooi Lim , Hee Kong Phoon
发明人： Chee Hak Teh , Chee Seng Leong , Lai Guan Tang , Han Wooi Lim , Hee Kong Phoon
IPC分类号： H01L23/528 , H01L23/498 , H03K19/177
摘要： The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

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