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1. 发明申请

US20060182214A1 Methods to self-synchronize clocks on multiple chips in a system 失效
标题翻译：在系统中的多个芯片上自动同步时钟的方法
公开(公告)号：US20060182214A1
公开(公告)日：2006-08-17
申请号：US11056767
申请日：2005-02-11
申请人： Charlie Hwang , Timothy McNamara , Ching-Lung Tong , Wiren Becker
发明人： Charlie Hwang , Timothy McNamara , Ching-Lung Tong , Wiren Becker
IPC分类号： H04L7/02
CPC分类号： H03L7/06 , G06F1/10
摘要： A method of self-synchronizing clocks in a multiple chip system, by assigning one chip as the master chip and the other chips as slave chips. A training signal is sent from master chip to the slave chips to determine the latency from the master chip to a slave chip, and then a synchronization signal is sent out to synchronize the “time zero” of the chips.
摘要翻译：一种在多芯片系统中自同步时钟的方法，通过分配一个芯片作为主芯片，将其它芯片分配为从芯片。训练信号从主芯片发送到从芯片，以确定从主芯片到从芯片的延迟，然后发送同步信号以同步芯片的“时间零”。

2. 发明申请

US20060182212A1 Method and apparatus for generating synchronization signals for synchronizing multiple chips in a system 失效
标题翻译：用于产生用于同步系统中的多个芯片的同步信号的方法和装置
公开(公告)号：US20060182212A1
公开(公告)日：2006-08-17
申请号：US11363871
申请日：2006-02-28
申请人： Charlie Hwang , Wiren Becker , Timothy McNamara , Ching-Lung Tong
发明人： Charlie Hwang , Wiren Becker , Timothy McNamara , Ching-Lung Tong
IPC分类号： H04L7/00
CPC分类号： G06F1/10 , H03L7/06
摘要： A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically. This invention resolves the uncertainty problem and allows the synchronization signals to be generated deterministically independent of the chip global clock cycle time
摘要翻译：一种用于产生多芯片系统的同步信号的时钟发生器电路。时钟发生器电路包括从参考时钟和具有边缘检测逻辑的芯片全局时钟产生同步信号。在具有多个芯片的高性能服务器系统设计中，服务器系统的常见做法是使用反馈时钟和延迟参考时钟来生成同步信号。所产生的同步信号被传送到由全局时钟计时的锁存器，以用于芯片同步功能。随着系统时钟频率被推高，由反馈时钟所产生的所生成的同步信号与由全局时钟计时的接收锁存器之间的相位差成为这个信号不能被确定地传送的循环时间的大部分。本发明解决了不确定性问题，并允许确定地产生同步信号，而不依赖于芯片全局时钟周期时间

3. 发明申请

US20070176651A1 Circuits for locally generating non-integral divided clocks with centralized state machines 失效
标题翻译：用集中式状态机本地生成非积分分时钟的电路
公开(公告)号：US20070176651A1
公开(公告)日：2007-08-02
申请号：US11341032
申请日：2006-01-27
申请人： William Huott , Charlie Hwang , Timothy McNamara
发明人： William Huott , Charlie Hwang , Timothy McNamara
IPC分类号： H03K23/00
CPC分类号： H03K23/502
摘要： Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles. The state machine generates a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal, the clock high signal and the clock low signal having patterns derived from a waveform of a target divided ratio clock, the clock high signal and the clock low signals have patterns that match the targeted divided clock frequency and duty cycle. A local pass gate receives the clock low signal and the clock high signal and generates an (n+0.5)-to−1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.
摘要翻译：用于在芯片上本地生成比率时钟的电路。该电路包括用于产生具有全局时钟周期的全局时钟信号的电路。状态机包括响应于非整数个全局时钟周期的整个周期的计数器。状态机响应于计数器产生控制信号。分段锁存器接收控制信号并产生时钟高信号和时钟低信号，时钟高信号和时钟低信号具有从目标分频比时钟的波形导出的模式，时钟高信号和时钟低信号具有符合目标分频时钟频率和占空比的模式。本地通过门接收时钟低电平信号和时钟高电平信号，并响应于全局时钟信号，时钟高电平信号和时钟低电平信号产生（n + 0.5）至1时钟信号。

4. 发明申请

US20070176653A1 METHODS AND SYSTEMS FOR LOCALLY GENERATING NON-INTEGRAL DIVIDED CLOCKS WITH CENTRALIZED STATE MACHINES 失效
标题翻译：用集中式状态机定位生成非整体分时钟的方法与系统
公开(公告)号：US20070176653A1
公开(公告)日：2007-08-02
申请号：US11419224
申请日：2006-05-19
申请人： William Huott , Charlie Hwang , Timothy McNamara
发明人： William Huott , Charlie Hwang , Timothy McNamara
IPC分类号： H03K23/00
CPC分类号： G06F7/68 , H03K23/68
摘要： A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal. Local pass gates generate an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.
摘要翻译：用于在芯片上本地产生比率时钟的方法包括产生具有全局时钟周期的全局时钟信号。集中式状态机包括响应于非整数数量的全局时钟周期的整个周期的计数器，状态机响应于计数器产生控制信号。控制信号被提供给分段锁存器，分段锁存器产生时钟高信号和时钟低电平信号。响应于全局时钟信号，时钟高电平信号和时钟低电平信号，本地通道门产生（n + 0.5）至1时钟信号。

5. 发明申请

US20080030246A1 Circuits for Locally Generating Non-Integral Divided Clocks with Centralized State Machines 审中-公开
标题翻译：用集中式机器本地生成非积分分时钟的电路
公开(公告)号：US20080030246A1
公开(公告)日：2008-02-07
申请号：US11869935
申请日：2007-10-10
申请人： William Huott , Charlie Hwang , Timothy McNamara
发明人： William Huott , Charlie Hwang , Timothy McNamara
IPC分类号： H03L7/00
CPC分类号： H03K23/502
摘要： Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal. A local pass gate receives the clock low signal and the clock high signal and generating an (n+0.5)-to-1 clock signal in response to at least one of the global clock signal, the clock high signal and the clock low signal.
摘要翻译：用于在芯片上本地生成比率时钟的电路。该电路包括用于产生具有全局时钟周期的全局时钟信号的电路。状态机包括响应于非整数个全局时钟周期而经过整个周期的计数器，状态机响应于计数器产生控制信号。分段锁存器接收控制信号并产生时钟高电平信号和时钟低电平信号。响应于全局时钟信号，时钟高电平信号和时钟低电平信号中的至少一个，本地通道门接收时钟低电平信号和时钟高电平信号并产生（n + 0.5）至1时钟信号。

6. 发明申请

US20070176652A1 Method for locally generating non-integral divided clocks with centralized state machines 失效
标题翻译：用集中式状态机本地生成非积分分时钟的方法
公开(公告)号：US20070176652A1
公开(公告)日：2007-08-02
申请号：US11341038
申请日：2006-01-27
申请人： William Huott , Charlie Hwang , Timothy McNamara
发明人： William Huott , Charlie Hwang , Timothy McNamara
IPC分类号： H03K23/00
CPC分类号： H03K23/68 , G06F7/68
摘要： A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine is provided that includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the centralized state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal, the clock high and clock low signal having patterns derived from a waveform of a target divided ratio clock and the clock high and clock low signals have patterns that match the targeted divided clock frequency and duty cycle. Local pass gate are provided for generating an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.
摘要翻译：用于在芯片上本地产生比率时钟的方法包括产生具有全局时钟周期的全局时钟信号。提供集中式状态机，其包括响应于非整数数量的全局时钟周期的整个周期的计数器，所述集中式状态机响应于所述计数器产生控制信号。控制信号被提供给分段锁存器，分段锁存器产生时钟高信号和时钟低信号，时钟高电平和时钟低电平信号具有从目标分频比时钟的波形导出的模式，以及时钟高电平和时钟低电平信号具有匹配目标分频时钟频率和占空比的模式。本地通路门用于响应于全局时钟信号，时钟高电平信号和时钟低电平信号产生（n + 0.5）至1时钟信号。

7. 发明申请

US20070229115A1 Method and apparatus for correcting duty cycle error in a clock distribution network 审中-公开
标题翻译：用于校正时钟分配网络中的占空比误差的方法和装置
公开(公告)号：US20070229115A1
公开(公告)日：2007-10-04
申请号：US11339124
申请日：2006-01-25
申请人： Charlie Hwang , Phillip Restle , Michael Thomson
发明人： Charlie Hwang , Phillip Restle , Michael Thomson
IPC分类号： H03M7/00 , H03K19/00
CPC分类号： H03K5/1565 , G06F1/10 , H03K5/065
摘要： A clock distribution network for distributing a repetitive timing signal throughout an integrated circuit, the timing signal being within a range of frequencies about a first frequency, includes multiple buffer circuits and at least one conductive segment connecting one of the buffers to another of the buffers. The conductive segment has a length selected so as to be less than a quarter-wave resonance length of the conductive segment at the first frequency to thereby achieve duty cycle correction.
摘要翻译：一种用于在整个集成电路中分配重复定时信号的时钟分配网络，定时信号在大约关于第一频率的频率范围内，包括多个缓冲器电路和至少一个将缓冲器之一连接到另一个缓冲器的导电段。导电段的长度被选择为小于第一频率处的导电段的四分之一波长的谐振长度，从而实现占空比校正。

8. 发明申请

US20050132314A1 Circuits and methods for matching device characteristics for analog and mixed-signal designs 失效
标题翻译：用于匹配模拟和混合信号设计的器件特性的电路和方法
公开(公告)号：US20050132314A1
公开(公告)日：2005-06-16
申请号：US10733079
申请日：2003-12-11
申请人： Howard Chen , Louis Hsu , Charlie Hwang
发明人： Howard Chen , Louis Hsu , Charlie Hwang
IPC分类号： H01L21/822 , G06F9/45 , G06F17/50 , H01L21/82 , H01L27/04 , H01L27/118
CPC分类号： G06F17/5068
摘要： Circuit designs and methods are provided for matching device characteristics for, e.g., analog or mixed-signal semiconductor integrated circuit designs. In particular, circuit layout patterns and layout methods are provided which enable precise or proportional matching of circuit components by uniformly distributing circuit components in a manner that eliminates or significantly minimizes the sensitivity of such circuit components to environmental effects and process variations, thereby improving the performance of analog and mixed-signal circuits.
摘要翻译：提供电路设计和方法用于匹配例如模拟或混合信号半导体集成电路设计的器件特性。特别地，提供电路布局图案和布局方法，其通过以消除或显着地最小化这些电路部件对环境影响和工艺变化的灵敏度的方式均匀地分配电路部件来实现电路部件的精确或比例匹配，从而提高性能的模拟和混合信号电路。

9. 发明申请

US20050246125A1 System And Method Of Digitally Testing An Analog Driver Circuit 失效
标题翻译：数字测试模拟驱动电路的系统和方法
公开(公告)号：US20050246125A1
公开(公告)日：2005-11-03
申请号：US10708788
申请日：2004-03-25
申请人： Joseph Marsh , Jeremy Stephens , Charlie Hwang , James Mason , Huihao Xu , Matthew Baecher , Thomas Bardsley , Mark Taylor
发明人： Joseph Marsh , Jeremy Stephens , Charlie Hwang , James Mason , Huihao Xu , Matthew Baecher , Thomas Bardsley , Mark Taylor
IPC分类号： G01R31/3167 , G01R31/3185 , G06F19/00
CPC分类号： G01R31/3167 , G01R31/318544
摘要： A circuit and method of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention comprises a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal in response to the differential input signal and the signals generated by the control circuit, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit in response the signals generated by the control circuit, and a differential receiver circuit for receiving the differential output from the differential driver circuit, convert the differential output signal to a single ended signal and transmitting the single ended signal, all in response to the test enable signal. The method of the present invention comprises digitally testing the differential driver circuit by activating a test enable signal, skewing the differential output termination impedance in response to the test enable signal, adjusting a voltage offset of the differential receiver circuit in response to the test enable signal, selecting a power level for the differential driver circuit in response to the test enable signal, enabling a decoder in response to the test enable signal, wherein the decoder activates only one segment of the differential driver circuit during any one test sequence, activating one of the segments for testing, stimulating the differential driver circuit with digital test patterns, receiving an output of the differential driver circuit by the differential receiver circuit, converting the received differential driver output to a single-ended signal, observing the single-ended signal; and deactivating the test enable signal.
摘要翻译：使用基于数字扫描的测试方法测试模拟驱动器电路的电路和方法。本发明的电路包括用于响应于测试使能信号产生信号的控制电路，用于接收差分输入信号的差分驱动器电路，放大差分输入信号并响应差分输入信号发送差分输出信号以及由所述控制电路产生的信号，用于响应于由所述控制电路产生的信号而在所述差分驱动器电路的输出节点处产生差分终端阻抗的可编程终端阻抗电路以及用于从所述差分接收电路接收所述差分输出的差分接收电路差分驱动器电路将差分输出信号转换为单端信号并传输单端信号，全部是响应于测试使能信号。本发明的方法包括通过激活测试使能信号来数字测试差分驱动器电路，响应于测试使能信号偏移差动输出终端阻抗，响应于测试使能信号调整差分接收器电路的电压偏移，响应于所述测试使能信号选择所述差分驱动器电路的功率电平，使能够响应于所述测试使能信号的解码器，其中所述解码器在任何一个测试序列期间仅激活所述差分驱动器电路的一个部分，用于测试的段，用数字测试图案刺激差分驱动器电路，通过差分接收器电路接收差分驱动器电路的输出，将接收到的差分驱动器输出转换为单端信号，观察单端信号; 并禁用测试使能信号。

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