会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明授权
    • Hybrid instantaneous frequency measurement compressive receiver
apparatus and method
    • 混合瞬时频率测量压缩接收机装置及方法
    • US5424631A
    • 1995-06-13
    • US176705
    • 1994-01-03
    • Charles R. Ward
    • Charles R. Ward
    • G01R23/175G01S7/02G01R23/00
    • G01R23/175G01S7/021
    • The present invention hybrid instantaneous frequency measurement (IFM) compressive receiver processes a wide bandwidth of incoming signals in two processing channels, where a small time delay is introduced to one of the two channels by a time delay stage. A comb generator provides for folding, or collapsing this wide input band into a much narrower bandwidth by overlapping sub-bands of the input band in the same frequency space. A compressive receiver is coupled to the spectrum folding circuitry for accurately measuring the frequency and amplitude of signals in this folded band, which have a sub-band ambiguity due to the folding. Logic circuitry is included for resolving the sub-band ambiguity in order to provide a unique description of the frequencies of input signals in the wide band input frequency range. The hybrid receiver overcomes the limitations of conventional IFM receivers by providing amplitude as well as frequency information for multiple time overlapped input signals with improved sensitivity. It also overcomes the limitations of a conventional compressive receiver by handling much wider input bandwidths than would otherwise be possible.
    • 本发明的混合瞬时频率测量(IFM)压缩接收机在两个处理信道中处理输入信号的宽带宽,其中通过时间延迟阶段将小的时间延迟引入到两个信道之一中。 梳状发生器通过在相同频率空间中重叠输入频带的子带,来将该宽输入频带折叠或折叠成更窄的带宽。 压缩接收器耦合到频谱折叠电路,用于精确地测量该折叠带中的信号的频率和幅度,由于折叠而具有子带模糊性。 包括逻辑电路用于解决子带模糊度,以便提供宽带输入频率范围内输入信号频率的唯一描述。 混合接收机通过提供具有改善的灵敏度的多个重叠输入信号的幅度以及频率信息来克服常规IFM接收机的局限性。 它还克服了常规压缩接收机通过处理比其他可能的更宽的输入带宽的限制。
    • 3. 发明授权
    • Processor for multiple, continuous, spread spectrum signals
    • 处理器用于多个连续的扩频信号
    • US4164628A
    • 1979-08-14
    • US887708
    • 1978-03-17
    • Charles R. WardRobert A. Reilly
    • Charles R. WardRobert A. Reilly
    • H04B1/7093H04J13/00
    • H04B1/7093H04B2201/70707
    • This relates to a signal processor which accepts the linear sum of several continuous (CW) direct sequence, spread spectrum signals, and outputs a sequence of narrow pulses, each of which contains all the available energy of one of the input signals. The CW signals are applied to the input of a tapped delay line, the contents of which are compared, in a parallel fashion, with the output of a code storage register. When correlation has been achieved, a narrow pulse is produced which contains all the available energy of one of the input signals. The circuit reduces the problem of continuously processing several simultaneous signals, conventionally performed with dedicated circuitry for each signal, to a sequential pulse processing operation, effectively timesharing the same single set of circuitry. Both amplitude and phase information is preserved through the processing technique allowing implementation in coherent and non-coherent system architectures.
    • 这涉及一种信号处理器,其接受几个连续(CW)直接序列,扩频信号的线性和,并且输出一系列窄脉冲,每个窄脉冲包含输入信号之一的所有可用能量。 将CW信号以并行的方式与代码存储寄存器的输出相加,并将其内容应用于抽头延迟线的输入。 当已经实现相关时,产生包含输入信号之一的所有可用能量的窄脉冲。 该电路减少了将通常用专用电路执行的几个同时信号连续处理到顺序脉冲处理操作的问题,该操作有效地对共同的单组电路进行时分。 通过处理技术保持幅度和相位信息,允许在相干和非相干系统架构中实现。
    • 7. 发明授权
    • Agile code generator
    • 敏捷代码生成器
    • US4142240A
    • 1979-02-27
    • US829382
    • 1977-08-31
    • Charles R. WardRobert A. Reilly
    • Charles R. WardRobert A. Reilly
    • G06F7/58G06F7/00
    • G06F7/584G06F2207/581
    • The code generator of the present invention uses digital memories to replace the linear feedback shift registers of the prior art. Each memory contains the time ordered bit sequence for each of the component codes which in general, make up the overall, longer code. Since the entire bit sequences of the component codes are immediately available in the memories by appropriate addressing, the code generator can be initialized to an arbitrary, but defined code state within the response time of the memory element. As an additional benefit, at the option of the designer, the digital memory can be chosen to extract code segments, for example, 8 bits wide rather than single bits, and this parallel approach reduces code clocking speed through much of the code generator hardware, and/or may permit several code patterns for multichannel applications to be constructed using the same common memories.
    • 本发明的代码生成器使用数字存储器来代替现有技术的线性反馈移位寄存器。 每个存储器包含每个组件代码的时间排序比特序列,其通常构成整体较长的代码。 由于组件代码的整个比特序列通过适当的寻址在存储器中立即可用,所以代码生成器可以在存储器元件的响应时间内被初始化为任意但是定义的代码状态。 作为额外的好处,作为设计者的选择,可以选择数字存储器来提取代码段,例如8位宽而不是单个位,并且这种并行方法通过大量代码生成器硬件来降低代码时钟速度, 和/或可以允许使用相同的公共存储器构造用于多通道应用的多个代码模式。