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1. 发明授权

US4554627A Data processing system having a unique micro-sequencing system 失效
标题翻译：数据处理系统具有独特的微测序系统
公开(公告)号：US4554627A
公开(公告)日：1985-11-19
申请号：US473560
申请日：1983-03-09
申请人： Charles J. Holland , Kenneth D. Holberger , David I. Epstein , Paul Reilly , Josh Rosen
发明人： Charles J. Holland , Kenneth D. Holberger , David I. Epstein , Paul Reilly , Josh Rosen
IPC分类号： G06F9/26 , G06F9/318 , G06F11/10 , G06F11/14 , G06F12/08 , G06F12/10 , G06F12/14 , G06F13/00
CPC分类号： G06F9/3017 , G06F11/10 , G06F11/14 , G06F12/0802 , G06F12/0857 , G06F12/1009 , G06F12/14 , G06F9/26 , G06F11/106
摘要： A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit.
摘要翻译：一种数据处理系统，其处理可从十六位逻辑地址或三十二位逻辑地址导出的二十二位逻辑地址，后者通过唯一的转换装置转换成物理地址。该系统包括用于解码基本指令集和扩展指令集的宏指令的装置，每个宏指令本身都包含唯一地标识要被解码的指令类型的所选位模式。解码的宏指令提供一个或多个微指令的起始地址，该地址被提供给唯一的微指令排序单元，其适当地解码每个微指令的选定字段以获得每个连续的微指令。该系统使用八个存储段（环）的分层存储器存储，根据不同级别的权限访问以特权方式控制的环。存储器系统使用一组主存储器模块，其通过双端口高速缓冲存储器与中央处理器系统连接，在主存储器和高速缓冲存储器之间块数据传输由存储体控制器单元控制。

2. 发明授权

US4386399A Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：US4386399A
公开(公告)日：1983-05-31
申请号：US143561
申请日：1980-04-25
申请人： Edward Rasala , Steven Wallach , Carl J. Alsing , Kenneth D. Holberger , Charles J. Holland , Thomas West , James M. Guyer , Richard W. Coyle , Michael L. Ziegler , Michael B. Druke
发明人： Edward Rasala , Steven Wallach , Carl J. Alsing , Kenneth D. Holberger , Charles J. Holland , Thomas West , James M. Guyer , Richard W. Coyle , Michael L. Ziegler , Michael B. Druke
IPC分类号： G06F9/22 , G06F9/26 , G06F9/30 , G06F9/34 , G06F11/10 , G06F11/14 , G06F12/08 , G06F12/10 , G06F12/14 , G06F13/00 , G06F9/36
CPC分类号： G06F12/0857 , G06F11/10 , G06F11/14 , G06F12/0802 , G06F12/1009 , G06F12/14 , G06F9/26 , G06F9/3013 , G06F9/30185 , G06F9/30196 , G06F9/342 , G06F11/106
摘要： A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit.
摘要翻译：一种数据处理系统，其处理可从十六位逻辑地址或三十二位逻辑地址导出的二十二位逻辑地址，后者通过唯一的转换装置转换成物理地址。该系统包括用于解码基本指令集和扩展指令集的宏指令的装置，每个宏指令本身都包含唯一地标识要被解码的指令类型的所选位模式。解码的宏指令提供一个或多个微指令的起始地址，该地址被提供给唯一的微指令排序单元，其适当地解码每个微指令的选定字段以获得每个连续的微指令。该系统使用八个存储段（环）的分层存储器存储，根据不同级别的权限访问以特权方式控制的环。存储器系统使用一组主存储器模块，其通过双端口高速缓冲存储器与中央处理器系统连接，在主存储器和高速缓冲存储器之间块数据传输由存储体控制器单元控制。

3. 发明授权

US4679138A Microsequencer in a data processing system using stack storage for controlling the sequencing of microroutines 失效
标题翻译：数据处理系统中的微定序器使用堆栈存储来控制微阵列的排序
公开(公告)号：US4679138A
公开(公告)日：1987-07-07
申请号：US256714
申请日：1981-04-23
申请人： David I. Epstein , Charles J. Holland
发明人： David I. Epstein , Charles J. Holland
IPC分类号： G06F9/22
CPC分类号： G06F9/226
摘要： A data processing system in which macroinstructions are decoded to provide a sequence of microinstructions comprising one or more microroutines. A stack storage means stores data for use in such microroutines. The final microinstruction of the microroutines is a request to retrieve or remove data from the stack. When no data is present therein (the stack is empty) a new macroinstruction is requested and when data is present in the stack the microroutine returns to another mircoroutine in which it is acting as a micro-subsroutine to permit continuation of the other microroutine.
摘要翻译：数据处理系统，其中宏指令被解码以提供包括一个或多个微阵列的微指令序列。堆栈存储装置存储用于这样的微程序的数据。微程序的最终微指令是从堆栈中检索或删除数据的请求。当其中没有数据（堆栈为空）时，请求一个新的宏指令，并且当数据存在于堆栈中时，微循环返回到另一个微循环，其中它作为微子程序，以允许其他微程序的继续。

4. 发明授权

US4434459A Data processing system having instruction responsive apparatus for both a basic and an extended instruction set 失效
标题翻译：具有用于基本和扩展指令集的指令响应装置的数据处理系统
公开(公告)号：US4434459A
公开(公告)日：1984-02-28
申请号：US143982
申请日：1980-04-25
申请人： Charles J. Holland , Steven Wallach , Carl J. Alsing
发明人： Charles J. Holland , Steven Wallach , Carl J. Alsing
IPC分类号： G06F9/26 , G06F9/318 , G06F9/38 , G06F9/48 , G06F11/10 , G06F12/14 , G06F9/00
CPC分类号： G06F9/4812 , G06F11/10 , G06F12/1491 , G06F9/268 , G06F9/3017 , G06F9/30181 , G06F9/30196 , G06F9/3822 , G06F11/106
摘要： A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The instruction responsive apparatus thereof responds to unique microinstructions which, for example, provide for the selection of one of a plurality of interrupt routines each corresponding to an interrupt request from a different external device, provide for the sequential loading of a plurality of segment identification registers each pointing to selected memory management tables associated with a segment storage region of main memory, provide for a program counter relative jump operation, provide for zero-extending or sign-extending 16-bit words to 32-bit words having the same value, and provide for the multiplication of the lower 16 bits of two 32-bit accumulators and the sign-extension of the 16-bit result to form a 32-bit word.
摘要翻译：一种数据处理系统，其处理可从十六位逻辑地址或三十二位逻辑地址导出的二十二位逻辑地址，后者通过唯一的转换装置转换成物理地址。该系统包括用于解码基本指令集和扩展指令集的宏指令的装置，每个宏指令本身都包含唯一地标识要被解码的指令类型的所选位模式。其指令响应装置响应于唯一的微指令，其例如提供对来自不同外部设备的中断请求的多个中断程序中的一个的选择，提供多个段识别寄存器的顺序加载每个指向与主存储器的段存储区域相关联的选择的存储器管理表，提供程序计数器相对跳转操作，向具有相同值的32位字提供零扩展或符号扩展16位字，以及提供两个32位累加器的低16位的乘法和16位结果的符号扩展以形成32位字。

5. 发明授权

US5604862A Continuously-snapshotted protection of computer files 失效
标题翻译：持续快照保护计算机文件
公开(公告)号：US5604862A
公开(公告)日：1997-02-18
申请号：US403347
申请日：1995-03-14
申请人： Christopher W. Midgely , Charles J. Holland , John W. Webb , Manuel Gonsalves
发明人： Christopher W. Midgely , Charles J. Holland , John W. Webb , Manuel Gonsalves
IPC分类号： G06F11/14 , G06F11/34
CPC分类号： G06F11/1448 , G06F11/3476 , G06F2201/84
摘要： An Integrity Server computer for economically protecting the data of a computer network's servers, and providing hot standby access to up-to-date copies of the data of a failed server. As the servers' files are created or modified, they are copied to the Integrity Server. The invention provides novel methods for managing the data stored on the Integrity Server, so that up-to-date snapshots of files of the protected file servers are stored on low-cost media such as tape, but without requiring that a system manager load large numbers of tapes.
摘要翻译： Integrity Server计算机，用于经济地保护计算机网络服务器的数据，并为故障服务器的数据的最新副本提供热备份访问。随着服务器的文件被创建或修改，它们被复制到Integrity服务器。本发明提供用于管理存储在Integrity服务器上的数据的新颖方法，使得受保护文件服务器的文件的最新快照存储在诸如磁带的低成本介质上，但不要求系统管理器负载大磁带数量

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