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1. 发明授权

US5611062A Specialized millicode instruction for string operations 失效
标题翻译：用于字符串操作的专用millicode指令
公开(公告)号：US5611062A
公开(公告)日：1997-03-11
申请号：US414961
申请日：1995-03-31
申请人： Charles F. Webb , Mark S. Farrell , Christopher R. Conklin , Wen H. Li
发明人： Charles F. Webb , Mark S. Farrell , Christopher R. Conklin , Wen H. Li
IPC分类号： G06F9/308 , G06F9/318 , G06F7/04
CPC分类号： G06F9/30018 , G06F9/3017
摘要： Special millicode instructions accelerate the "inner loop" portion of a millicode routine to execute ESA/390 string instructions. Specifically, these millicode instructions are: Replicate Byte, Find Byte Equal, Find Byte Not Equal, Compare String Bytes instructions.
摘要翻译：特殊的millicode指令加速了一个millicode例程的“内部循环”部分来执行ESA / 390字符串指令。具体来说，这些millicode指令是：复制字节，查找字节等于，查找字节不相等，比较字符串字节指令。

2. 发明授权

US5621909A Specialized millicode instruction for range checking 失效
标题翻译：专用millicode指令进行范围检查
公开(公告)号：US5621909A
公开(公告)日：1997-04-15
申请号：US614148
申请日：1996-03-12
申请人： Charles F. Webb , Mark S. Farrell , Wen H. Li
发明人： Charles F. Webb , Mark S. Farrell , Wen H. Li
IPC分类号： G06F9/30 , G06F9/32 , G06F9/00
CPC分类号： G06F9/30021 , G06F9/30094
摘要： A range check instruction sequence, which performs a logical comparison between two 32-bit values and updates the condition code as a result. It operates identically to the ESA/390 instruction compare logical (CLR) except for the way in which the condition code is set. The new condition code is a function of both the comparison result and the previous condition code. If the first operand is greater than the second operand, the condition code remains unchanged. If the first operand is less than or equal to the second operand, the condition code is set to 2 if it was previously 0 or 1, and is set to 3 if it was previously 2 or 3. This may be understood as advancing the state of the condition code among the groups (0,1), 2, and 3 if the first operand is not greater than the second operand.
摘要翻译：范围检查指令序列，其执行两个32位值之间的逻辑比较，并作为结果更新条件代码。除了条件码的设置方式以外，它与ESA / 390指令比较逻辑（CLR）相同。新条件代码是比较结果和先前条件代码的函数。如果第一个操作数大于第二个操作数，则条件代码保持不变。如果第一个操作数小于或等于第二个操作数，则如果先前为0或1，则条件代码设置为2，如果先前为2或3，则将其设置为3。这可以被理解为推进状态如果第一个操作数不大于第二个操作数，组（0,1），2和3中的条件代码。

3. 发明授权

US08078843B2 Facilitating processing in a computing environment using an extended drain instruction 有权
标题翻译：在计算环境中利用扩展的漏极指令促进处理
公开(公告)号：US08078843B2
公开(公告)日：2011-12-13
申请号：US12023155
申请日：2008-01-31
申请人： Khary J. Alexander , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Timothy J. Slegel , Charles F. Webb
发明人： Khary J. Alexander , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F9/30
CPC分类号： G06F9/30079 , G06F9/30145 , G06F9/3867
摘要： An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired. The enhanced DRAIN instruction enables its use to be more granular and to have minimal impact with respect to each individual use.
摘要翻译：扩展DRAIN指令用于在计算环境中停止处理。该指令包括处理被停止的一个或多个处理阶段的指示。它还包括一个控制，允许根据需要使处理停滞在额外的周期。增强的DRAIN指令使其使用更细致，对每个用户的影响最小。

4. 发明授权

US07712076B2 Register indirect access of program floating point registers by millicode 失效
标题翻译：通过millicode寄存器间接访问程序浮点寄存器
公开(公告)号：US07712076B2
公开(公告)日：2010-05-04
申请号：US11531301
申请日：2006-09-13
申请人： Steven R. Carlough , Mark S. Farrell , Eric M. Schwarz , Timothy J. Slegel , Charles F. Webb
发明人： Steven R. Carlough , Mark S. Farrell , Eric M. Schwarz , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F9/44
CPC分类号： G06F9/3017 , G06F9/35
摘要： Complex floating point instructions are executed under millicode control when it is not cost effective to implement its function in hardware. One of the disadvantages to executing complex instructions using millicode routines is that determining and accessing the instructions operands are costly for millicode performance. To determine what the source and target location are, the instruction text is parsed. Furthermore the millicode instruction stream must be modified to access the operand data from and write the result to the program registers specified by the complex floating point instruction. The invention overcomes these disadvantages by providing millicode with register indirect access to the program floating point registers.
摘要翻译：当在硬件中实现其功能不具有成本效益时，复杂的浮点指令在毫秒控制下执行。使用millicode例程执行复杂指令的一个缺点是确定和访问指令操作数对于millicode性能来说是昂贵的。要确定源和目标位置是什么，解释说明文本。此外，必须修改millicode指令流以访问操作数数据，并将结果写入由复杂浮点指令指定的程序寄存器。本发明通过向编程浮点寄存器提供寄存器间接访问的毫代码来克服这些缺点。

5. 发明申请

US20080126759A1 Register Indirect Access of Program Floating Point Registers by Millicode 失效
标题翻译：通过Millicode寄存器间接访问程序浮点寄存器
公开(公告)号：US20080126759A1
公开(公告)日：2008-05-29
申请号：US11531301
申请日：2006-09-13
申请人： Steven R. Carlough , Mark S. Farrell , Eric M. Schwarz , Timothy J. Slegel , Charles F. Webb
发明人： Steven R. Carlough , Mark S. Farrell , Eric M. Schwarz , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F9/302
CPC分类号： G06F9/3017 , G06F9/35
摘要： Complex floating point instructions are executed under millicode control when it is not cost effective to implement its function in hardware. One of the disadvantages to executing complex instructions using millicode routines is that determining and accessing the instructions operands are costly for millicode performance. To determine what the source and target location are, the instruction text is parsed. Furthermore the millicode instruction stream must be modified to access the operand data from and write the result to the program registers specified by the complex floating point instruction. The invention overcomes these disadvantages by providing millicode with register indirect access to the program floating point registers.
摘要翻译：当在硬件中实现其功能不具有成本效益时，复杂的浮点指令在毫秒控制下执行。使用millicode例程执行复杂指令的一个缺点是确定和访问指令操作数对于millicode性能来说是昂贵的。要确定源和目标位置是什么，解释说明文本。此外，必须修改millicode指令流以访问操作数数据，并将结果写入由复杂浮点指令指定的程序寄存器。本发明通过向编程浮点寄存器提供寄存器间接访问的毫代码来克服这些缺点。

6. 发明授权

US5625808A Read only store as part of cache store for storing frequently used millicode instructions 失效
标题翻译：只读存储作为缓存存储的一部分，用于存储常用的millicode指令
公开(公告)号：US5625808A
公开(公告)日：1997-04-29
申请号：US455820
申请日：1995-05-31
申请人： Charles F. Webb , Mark S. Farrell , Barry W. Krumm , John S. Liptay , Jennifer S. A. Navarro , Steven B. Risch , Mark A. Check
发明人： Charles F. Webb , Mark S. Farrell , Barry W. Krumm , John S. Liptay , Jennifer S. A. Navarro , Steven B. Risch , Mark A. Check
IPC分类号： G06F9/318 , G06F9/38 , G06F9/22
CPC分类号： G06F9/3802 , G06F9/3017
摘要： A read only storage (ROS) array holds a small set of relatively simple millicode instructions; those millicode instruction routines which are most commonly called on in executing common application workloads. The millicode read only store is implemented as a portion of hardware system area (HSA) storage. The cache control includes a register which contains hardware system area address corresponding to the read only store address. When an instruction fetch request is received by the cache control, the absolute address of the instruction fetch request is compared with the read only store address in the register in parallel with the normal cache directory lookup. If the instruction fetch request matches the read only store address, the fetch is made from the read only store independently of the directory lookup result.
摘要翻译：只读存储（ROS）阵列包含一小组相对简单的millicode指令; 那些在执行常见应用程序工作负载中最常调用的那些millicode指令例程。 millicode只读存储器实现为硬件系统区域（HSA）存储的一部分。高速缓存控制包括一个寄存器，该寄存器包含与只读存储地址对应的硬件系统区域地址。当缓存控制接收到指令提取请求时，将指令提取请求的绝对地址与正常缓存目录查找并行地与寄存器中的只读存储地址进行比较。如果指令提取请求与只读存储地址相匹配，则从独立于目录查找结果的只读存储进行读取。

7. 发明申请

US20090210662A1 MICROPROCESSOR, METHOD AND COMPUTER PROGRAM PRODUCT FOR DIRECT PAGE PREFETCH IN MILLICODE CAPABLE COMPUTER SYSTEM 有权
标题翻译： MICROPROCESSOR，方法和计算机程序产品，用于在MILLICODE可编程计算机系统中直接提取
公开(公告)号：US20090210662A1
公开(公告)日：2009-08-20
申请号：US12032041
申请日：2008-02-15
申请人： David A. Schroter , Mark S. Farrell , Jennifer Navarro , Chung-Lung Kevin Shum , Charles F. Webb
发明人： David A. Schroter , Mark S. Farrell , Jennifer Navarro , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F9/30 , G06F12/08
CPC分类号： G06F9/30047 , G06F12/0862
摘要： A microprocessor equipped to provide hardware initiated prefetching, includes at least one architecture for performing: issuance of a prefetch instruction; writing of a prefetch address into a prefetch fetch address register (PFAR); attempting a prefetch according to the address; detecting one of a cache miss and a cache hit; and if there is a cache miss, then sending a miss request to a next cache level and attempting cache access in a non-busy cycle; and if there is a cache hit, then incrementing the address in the PFAR and completing the prefetch. A method and a computer program product are provided.
摘要翻译：配备提供硬件发起预取的微处理器包括用于执行：发出预取指令的至少一个架构; 将预取地址写入预取提取地址寄存器（PFAR）; 根据地址尝试预取; 检测缓存未命中和缓存命中之一; 并且如果存在高速缓存未命中，则将错误请求发送到下一个高速缓存级别，并在非繁忙周期中尝试高速缓存访问; 并且如果存在缓存命中，则增加PFAR中的地址并完成预取。提供了一种方法和计算机程序产品。

8. 发明授权

US07478185B2 Directly initiating by external adapters the setting of interruption initiatives 有权
标题翻译：通过外部适配器直接启动中断计划的设置
公开(公告)号：US07478185B2
公开(公告)日：2009-01-13
申请号：US11620141
申请日：2007-01-05
申请人： Douglas G. Balazich , Michael D. Campbell , Janet R. Easton , Mark S. Farrell , Thomas A. Gregg , Kulwant M. Pandey , Gary E. Strait , Charles F. Webb
发明人： Douglas G. Balazich , Michael D. Campbell , Janet R. Easton , Mark S. Farrell , Thomas A. Gregg , Kulwant M. Pandey , Gary E. Strait , Charles F. Webb
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： The setting of interruption initiatives is directly initiated by external adapters. An adapter external to the processors at which the initiative is to be made pending sends a request directly to a system controller coupled to the adapter and the processors. The system controller then broadcasts a command to the processors instructing the processors to set the interruption initiative.
摘要翻译：中断计划的设置由外部适配器直接启动。处理器外部的适配器在外部的适配器将直接发送到耦合到适配器和处理器的系统控制器的请求。然后，系统控制器向指示处理器的处理器广播命令以设置中断主动性。

9. 发明授权

US07966474B2 System, method and computer program product for translating storage elements 有权
标题翻译：用于翻译存储元件的系统，方法和计算机程序产品
公开(公告)号：US07966474B2
公开(公告)日：2011-06-21
申请号：US12036520
申请日：2008-02-25
申请人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
发明人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
IPC分类号： G06F9/26
CPC分类号： G06F9/3017 , G06F9/30018 , G06F9/30101 , G06F9/355
摘要： A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.
摘要翻译：一种用于计算机系统中的翻译的系统，方法和计算机程序产品。该系统包括包含地址转换表的基地址的通用寄存器。该系统还包括被配置为接收多个要被翻译的元件的毫代可访问特殊位移寄存器。该系统还包括多路复用器，用于从毫代可访问特殊位移寄存器中选择多个元件中的特定元件，并用于产生位移或偏移值。该系统还包括地址发生器，用于创建包含来自通用寄存器的基地址和所生成的位移或偏移值的组合地址。

10. 发明授权

US06671793B1 Method and system for managing the result from a translator co-processor in a pipelined processor 有权
标题翻译：用于管理流水线处理器中的翻译协处理器的结果的方法和系统
公开(公告)号：US06671793B1
公开(公告)日：2003-12-30
申请号：US09678061
申请日：2000-10-02
申请人： Scott B. Swaney , Mark S. Farrell , John D. MacDougall , Hans-Juergen Muenster , Charles F. Webb
发明人： Scott B. Swaney , Mark S. Farrell , John D. MacDougall , Hans-Juergen Muenster , Charles F. Webb
IPC分类号： G06F1516
CPC分类号： G06F9/3017 , G06F9/3842 , G06F9/3861 , G06F9/3863 , G06F9/3879
摘要： An exemplary embodiment of the invention is a method and system for managing a result returned from a translator co-processor to a recovery unit of a central processor. The computer system has a pipelined computer processor and a pipelined central processor, which executes an instruction set in a hardware controlled execution unit and executes an instruction set in a milli-mode architected state with a millicode sequence of instructions in the hardware controlled execution unit. The central processor initiates a request to the translator co-processor a cycle after decode of a perform translator operation instruction in the millicode sequence. The translator co-processor processes the perform translator operation instruction to generate a perform translator operation result. The translator co-processor returns the results to a recovery unit of the central processor. The recovery unit stores the perform translator operation result in a system register. The request for the perform translator operation result by the central processor is interlocked by a hardware interlock of the recovery unit until the translator co-processor returns the perform translator operation result. The mechanism allows the recovery unit to maintain the correct perform translator operation result with speculative execution and instruction level retry recovery throughout the duration of the perform translator operation.
摘要翻译：本发明的示例性实施例是用于管理从翻译器协处理器返回到中央处理器的恢复单元的结果的方法和系统。计算机系统具有流水线计算机处理器和流水线中央处理器，其执行硬件控制执行单元中的指令集，并且在硬模式执行单元中以毫列指令序列执行毫模式架构状态指令集。中央处理器在解码执行转换器操作指令之后的一个循环中向转译器协处理器发出一个请求。翻译协处理器处理执行翻译器操作指令以产生执行转换器操作结果。翻译协处理器将结果返回到中央处理器的恢复单元。恢复单元将执行转换器操作结果存储在系统寄存器中。由中央处理器执行的执行转换器操作结果的请求由恢复单元的硬件互锁互锁，直到转换器协处理器返回执行转换器操作结果。该机制允许恢复单元在执行转换器操作的整个持续时间内通过推测执行和指令级重试恢复来维持正确的执行转换器操作结果。

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