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1. 发明申请

US20060261490A1 Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling 有权
公开(公告)号：US20060261490A1
公开(公告)日：2006-11-23
申请号：US11495057
申请日：2006-07-28
申请人： Chao-Yuan Su , Pei-Haw Tsao , Hsin-Hui Lee , Chender Huang , Shang Hou , Shin Jeng , Hao-Yi Tsai , Chenming Hu
发明人： Chao-Yuan Su , Pei-Haw Tsao , Hsin-Hui Lee , Chender Huang , Shang Hou , Shin Jeng , Hao-Yi Tsai , Chenming Hu
IPC分类号： H01L23/52
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area A1 is defined on the first scribe line and is defined by the equation A1=D1×S1, where D1 is the distance from the corner point of the die toward the main area of the die, and S1 is the width of the first scribe line. Free area AS is defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation AS=S1×S2, where S2 is the width of the second scribe line.

2. 发明授权

US07126225B2 Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling 有权
标题翻译：用于制造具有减少的分层和剥离的半导体晶片的装置和方法
公开(公告)号：US07126225B2
公开(公告)日：2006-10-24
申请号：US10675862
申请日：2003-09-30
申请人： Chao-Yuan Su , Pei-Haw Tsao , Hsin-Hui Lee , Chender Huang , Shang Y. Hou , Shin Puu Jeng , Hao-Yi Tsai , Chenming Hu
发明人： Chao-Yuan Su , Pei-Haw Tsao , Hsin-Hui Lee , Chender Huang , Shang Y. Hou , Shin Puu Jeng , Hao-Yi Tsai , Chenming Hu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area A1 is defined on the first scribe line and is defined by the equation A1=D1×S1, where D1 is the distance from the corner point of the die toward the main area of the die, and S1 is the width of the first scribe line. Free area AS is defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation AS=S1×S2, where S2 is the width of the second scribe line.
摘要翻译：具有限制测试键放置的自由区域的多层半导体结构。第一和第二划线相交以定义模具的一个角点。第一和第二划痕线是多层结构的一部分，多层结构的至少一层是低k电介质层。自由区域A 1 <1>在第一划线上被定义并且由等式1定义1 D 1 1 ，其中D <1> 是从模具的角点到模具的主要区域的距离，S 1是第一划线的宽度。在第一划线和与模具相邻的第二划线之间的交叉点处限定自由区域A＆S，并且由公式A S S = 其中S 2 <2>是第二划线的宽度。

3. 发明授权

US07294937B2 Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling 有权
标题翻译：用于制造具有减少的分层和剥离的半导体晶片的装置和方法
公开(公告)号：US07294937B2
公开(公告)日：2007-11-13
申请号：US11495057
申请日：2006-07-28
申请人： Chao-Yuan Su , Pei-Haw Tsao , Hsin-Hui Lee , Chender Huang , Shang Y. Hou , Shin Puu Jeng , Hao-Yi Tsai , Chenming Hu
发明人： Chao-Yuan Su , Pei-Haw Tsao , Hsin-Hui Lee , Chender Huang , Shang Y. Hou , Shin Puu Jeng , Hao-Yi Tsai , Chenming Hu
IPC分类号： H01L23/544
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area A1 is defined on the first scribe line and is defined by the equation A1=D1×S1, where D1 is the distance from the corner point of the die toward the main area of the die, and S1 is the width of the first scribe line. Free area AS is defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation AS=S1×S2, where S2 is the width of the second scribe line.
摘要翻译：具有限制测试键放置的自由区域的多层半导体结构。第一和第二划线相交以定义模具的一个角点。第一和第二划痕线是多层结构的一部分，多层结构的至少一层是低k电介质层。自由区域A 1 <1>在第一划线上被定义并且由等式1定义1 D 1 1 ，其中D <1> 是从模具的角点到模具的主要区域的距离，S 1是第一划线的宽度。在第一划线和与模具相邻的第二划线之间的交叉点处限定自由区域A＆S，并且由公式A S S = 其中S 2 <2>是第二划线的宽度。

4. 发明申请

US20060109014A1 Test pad and probe card for wafer acceptance testing and other applications 审中-公开
标题翻译：测试垫和探针卡，用于晶圆验收测试等应用
公开(公告)号：US20060109014A1
公开(公告)日：2006-05-25
申请号：US10996242
申请日：2004-11-23
申请人： Te-Tsung Chao , Chao-Yuan Su , Pei-Haw Tsao , Chender Huang
发明人： Te-Tsung Chao , Chao-Yuan Su , Pei-Haw Tsao , Chender Huang
IPC分类号： G01R31/02
CPC分类号： G01R31/2891 , G01R31/2884
摘要： A probe card having a member for sending and receiving electrical signals for operational testing of a semiconductor integrated circuit, and a plurality of probe pins extending from the member in a manner which causes free ends of the pins to contact wafer test pads substantially across a maximum dimension of the pads. Also, a test pad for a wafer or a substrate having a pad of electrically conductive material disposed in an area between seal rings of the wafer or substrate, the pad having a shape and/or a rotational orientation within the area between the seal rings that minimizes pad material immediately adjacent the seal rings. Further, a test pad for a wafer or substrate including a passivation layer disposed thereover, the test pad formed of a layer of electrically conductive material and disposed in an opening in the passivation layer, the opening disposed over an uppermost metal layer of the wafer or substrate, the opening and the test pad dimensioned so that the test pad does not contact the passivation layer. Still further, a protection structure for a wafer die core comprising a wafer including a passivation layer and a test pad extending through the passivation layer, and a trench in the passivation layer adjacent to an edge of the test pad.
摘要翻译：具有用于发送和接收用于半导体集成电路的操作测试的电信号的构件的探针卡，以及多个探针，所述探针从所述构件延伸，使得所述引脚的自由端基本上跨越最大值接触晶片测试垫垫的尺寸。此外，用于晶片或基板的测试焊盘，其具有设置在晶片或基板的密封环之间的区域中的导电材料焊盘，该焊盘在密封环之间的区域内具有形状和/或旋转取向，最小化紧邻密封环的垫材料。此外，包括设置在其上的钝化层的晶片或衬底的测试焊盘，所述测试焊盘由导电材料层形成并设置在钝化层的开口中，所述开口设置在晶片的最上层的金属层上，或衬底，开口和测试焊盘的尺寸设计成使得测试焊盘不接触钝化层。此外，晶片芯片的保护结构包括包括钝化层的晶片和延伸穿过钝化层的测试焊盘，以及钝化层中邻近测试焊盘边缘的沟槽。

5. 发明申请

US20060073635A1 Three dimensional package type stacking for thinner package application 审中-公开
标题翻译：三维包装类型堆叠为更薄的包装应用
公开(公告)号：US20060073635A1
公开(公告)日：2006-04-06
申请号：US10951428
申请日：2004-09-28
申请人： Chao-Yuan Su , Pei-Haw Tsao , Chender Huang
发明人： Chao-Yuan Su , Pei-Haw Tsao , Chender Huang
IPC分类号： H01L21/50
CPC分类号： H01L25/50 , H01L25/0657 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2924/15311 , H01L2924/15331 , H01L2924/00014 , H01L2924/00
摘要： A stacked semiconductor device, and method of making, having a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a first substrate. Solder balls are connected to contacts on the upper surface of the first substrate and a non-conductive layer is provided overlaying the first substrate and the first semiconductor chip. The solder balls are secured in cavities formed in the layer and extend beyond the top surface of the layer. A second semiconductor chip mounted on a second substrate is stacked on the layer with contacts on the lower surface of the second substrate in electrical contact with the extended portion of the solder balls, thereby connecting the second semiconductor chip with the first semiconductor chip.
摘要翻译：具有堆叠成一个封装的所需尺寸的多个半导体芯片的叠层半导体器件和制造方法安装在第一衬底上。焊球与第一基板的上表面上的触点连接，并且设置覆盖第一基板和第一半导体芯片的非导电层。焊球被固定在形成在层中的空腔中并且延伸超出该层的顶表面。安装在第二基板上的第二半导体芯片在第二基板的下表面上的触点层叠在与焊球的延伸部分电接触的层上，从而将第二半导体芯片与第一半导体芯片连接。

6. 发明申请

US20060065958A1 Three dimensional package and packaging method for integrated circuits 审中-公开
标题翻译：集成电路的三维封装和封装方法
公开(公告)号：US20060065958A1
公开(公告)日：2006-03-30
申请号：US10953045
申请日：2004-09-29
申请人： Pei-Haw Tsao , Chao-Yuan Su , Allan Lin , Frank Wu , Chender Huang
发明人： Pei-Haw Tsao , Chao-Yuan Su , Allan Lin , Frank Wu , Chender Huang
IPC分类号： H01L23/495
CPC分类号： H01L25/03 , H01L23/3128 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2924/01079 , H01L2924/01087 , H01L2924/15311 , H01L2924/19107 , H01L2924/00014 , H01L2924/00
摘要： A 3D package has: a three-dimensional (3D) package substrate, a land grid array (LGA) or quad flat no-lead (QFN) package mounted on the 3D package substrate, the LGA or QFN package having an LGA or QFN die on a first side of an LGA or QFN package substrate, and a second die mounted directly on a second side of the LGA or QFN package substrate opposite the first side.
摘要翻译： 3D封装具有：三维（3D）封装衬底，安装在3D封装衬底上的焊盘格子阵列（LGA）或四边形无引线（QFN）封装，具有LGA或QFN裸片的LGA或QFN封装在LGA或QFN封装衬底的第一侧上，以及直接安装在与第一侧相对的LGA或QFN封装衬底的第二侧上的第二管芯。

7. 发明授权

US07157734B2 Semiconductor bond pad structures and methods of manufacturing thereof 有权
标题翻译：半导体焊盘结构及其制造方法
公开(公告)号：US07157734B2
公开(公告)日：2007-01-02
申请号：US10908839
申请日：2005-05-27
申请人： Pei-Haw Tsao , Chender Huang , Shang-Yu Hou , Chao-Yuan Su , Chia-Hsiung Hsu
发明人： Pei-Haw Tsao , Chender Huang , Shang-Yu Hou , Chao-Yuan Su , Chia-Hsiung Hsu
IPC分类号： H01L23/58
CPC分类号： H01L24/05 , H01L22/32 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2224/04042 , H01L2224/05093 , H01L2224/05096 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4807 , H01L2224/48091 , H01L2224/48453 , H01L2224/48463 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48844 , H01L2224/48847 , H01L2224/85 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/10161 , H01L2924/14 , H01L2924/19041 , H01L2224/48824 , H01L2924/00 , H01L2224/48744
摘要： Described is a semiconductor device having improved semiconductor bond pad reliability and methods of manufacturing thereof. The semiconductor device includes a layer formed over an integrated circuit on a semiconductor substrate. The first layer includes a conductive portion and an insulating portion. A second layer is then formed over the first layer and includes a conductive portion corresponding to the first layer's conductive portion and an insulating portion corresponding to the first layer's insulating portion. A bond pad is then formed over the first and second layers such that the bond pad is substantially situated above the conductive portions and the insulating portions of the first and second layers. A bonding ball is then formed on the bond pad substantially above the conduction portion of the first and second layers.
摘要翻译：描述了具有改进的半导体接合焊盘可靠性的半导体器件及其制造方法。半导体器件包括在半导体衬底上的集成电路上形成的层。第一层包括导电部分和绝缘部分。然后在第一层上形成第二层，并且包括对应于第一层导电部分的导电部分和对应于第一层绝缘部分的绝缘部分。然后在第一层和第二层上形成接合焊盘，使得接合焊盘基本上位于第一层和第二层的导电部分和绝缘部分之上。然后在接合焊盘上形成基本上在第一和第二层的导电部分上方的接合球。

8. 发明申请

US20060091535A1 Fine pitch bonding pad layout and method of manufacturing same 审中-公开
标题翻译：细间距焊接布局及其制造方法
公开(公告)号：US20060091535A1
公开(公告)日：2006-05-04
申请号：US10904283
申请日：2004-11-02
申请人： Pei-Haw Tsao , Chao-Yuan Su , Chia Hsu , Chender Huang
发明人： Pei-Haw Tsao , Chao-Yuan Su , Chia Hsu , Chender Huang
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L24/06 , H01L22/32 , H01L2224/05552 , H01L2224/4943 , H01L2924/01028 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00012
摘要： Disclosed herein is a bonding pad formed on an IC chip for electrically coupling the IC chip to another device or component, and associated methods of manufacturing the bonding pad. In one embodiment, the bonding pad comprises a bonding portion having a bonding surface configured to receive an electrical connector. The bonding pad further comprises a probing portion having a probing surface adjacent and electrically coupled to the bonding surface, and configured to receive a probe tip for testing to the operation of the integrated circuit chip. In this embodiment, the bonding pad comprises a first planar dimension measured across the bonding portion and the adjacent probing portion, where the bonding portion further comprises a second planar dimension measured substantially perpendicular to the first planar dimension, and the probing portion comprises a third planar dimension measured substantially perpendicular to the first planar dimension and being less than the second planar dimension.
摘要翻译：这里公开了一种形成在用于将IC芯片电连接到另一个器件或部件的IC芯片上的焊盘，以及制造接合焊盘的相关方法。在一个实施例中，接合焊盘包括具有被配置为接收电连接器的接合表面的接合部分。接合焊盘还包括具有与接合表面相邻并电耦合的探测表面的探测部分，并且被配置为接收用于测试集成电路芯片的操作的探针尖端。在该实施例中，接合焊盘包括横跨接合部分和相邻探测部分测量的第一平面尺寸，其中接合部分还包括基本上垂直于第一平面尺寸测量的第二平面尺寸，并且探测部分包括第三平面尺寸基本上垂直于第一平面尺寸测量并且小于第二平面尺寸。

9. 发明申请

US20060076681A1 SEMICONDUCTOR PACKAGE SUBSTRATE FOR FLIP CHIP PACKAGING 审中-公开
标题翻译：用于芯片包装的半导体封装基板
公开(公告)号：US20060076681A1
公开(公告)日：2006-04-13
申请号：US10962455
申请日：2004-10-13
申请人： Pei-Haw Tsao , Chender Huang , Chao-Yuan Su
发明人： Pei-Haw Tsao , Chender Huang , Chao-Yuan Su
IPC分类号： H01L23/52 , H01L23/48 , H01L23/495
CPC分类号： H01L23/49816 , H01L23/49827 , H01L2924/0002 , H05K1/113 , H05K2201/09781 , H05K2201/2072 , H01L2924/00
摘要： A substrate of semiconductor package for flip chip package is provided. The substrate comprises a plurality of bump pads; a solder mask layer covering a portion of the plurality of bump pads; and a plurality of dummy anchor plugs coupled beneath the bump pads.
摘要翻译：提供了一种用于倒装芯片封装的半导体封装的衬底。衬底包括多个凸块焊盘; 覆盖所述多个凸块焊盘的一部分的焊料掩模层; 以及耦合在凸块焊盘下方的多个虚拟锚栓。

10. 发明申请

US20060043556A1 Stacked packaging methods and structures 审中-公开
标题翻译：堆叠包装方法和结构
公开(公告)号：US20060043556A1
公开(公告)日：2006-03-02
申请号：US10925488
申请日：2004-08-25
申请人： Chao-Yuan Su , Pei-Haw Tsao , Chender Huang
发明人： Chao-Yuan Su , Pei-Haw Tsao , Chender Huang
IPC分类号： H01L23/02
CPC分类号： H01L25/03 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/19107 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： A packaging method and structures are disclosed. A first die is mounted on a package substrate. A chip scale package is mounted on the first die. The chip scale package comprises a chip scale package substrate and a second die mounted on a first surface of the chip scale package substrate. A third die is mounted on a second surface of the chip scale package substrate. Accordingly, the height of the stacked package can be reduced.
摘要翻译：公开了一种包装方法和结构。第一管芯安装在封装衬底上。芯片级封装安装在第一裸片上。芯片级封装包括芯片级封装衬底和安装在芯片级封装衬底的第一表面上的第二裸片。第三裸片安装在芯片级封装衬底的第二表面上。因此，可以减小层叠包装的高度。

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