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1. 发明申请

US20100200974A1 SEMICONDUCTOR PACKAGE STRUCTURE USING THE SAME 审中-公开
标题翻译：使用相同的半导体封装结构
公开(公告)号：US20100200974A1
公开(公告)日：2010-08-12
申请号：US12505071
申请日：2009-07-17
申请人： Chao-Fu Weng , Tsung-Yueh Tsai , Chang-Ying Hung , Jen-Chieh Kao
发明人： Chao-Fu Weng , Tsung-Yueh Tsai , Chang-Ying Hung , Jen-Chieh Kao
IPC分类号： H01L23/52 , H01L23/49 , H01L23/28
CPC分类号： H01L24/05 , H01L23/3121 , H01L23/49811 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/04042 , H01L2224/05082 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/0516 , H01L2224/05164 , H01L2224/05166 , H01L2224/05181 , H01L2224/05639 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/32145 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48639 , H01L2224/48644 , H01L2224/48664 , H01L2224/48669 , H01L2224/48839 , H01L2224/48844 , H01L2224/48864 , H01L2224/73265 , H01L2225/06506 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/181 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2224/48869 , H01L2924/00012
摘要： A semiconductor package structure using the same is provided. The semiconductor package structure includes a first semiconductor element, a second semiconductor element, a binding wire and a molding compound. The first semiconductor element includes a semiconductor die and a pad. The pad is disposed above the semiconductor die and includes a metal base, a hard metal layer disposed above the metal base and an anti-oxidant metal layer disposed above the hard metal layer. The hardness of the hard metal layer is larger than that of the metal base. The activity of the anti-oxidant metal layer is lower than that of the hard metal layer. The first semiconductor element is disposed above the second semiconductor element. The bonding wire is connected to the pad and the second semiconductor element. The molding compound seals the first semiconductor element and the bonding wire and covers the second semiconductor element.
摘要翻译：提供了使用其的半导体封装结构。半导体封装结构包括第一半导体元件，第二半导体元件，绑定线和模制化合物。第一半导体元件包括半导体管芯和焊盘。焊盘设置在半导体管芯的上方，并且包括金属基底，设置在金属基底上方的硬金属层和设置在硬金属层上方的抗氧化金属层。硬质金属层的硬度大于金属基体的硬度。抗氧化金属层的活性低于硬质金属层的活性。第一半导体元件设置在第二半导体元件上方。接合线连接到焊盘和第二半导体元件。成型复合体密封第一半导体元件和接合线并覆盖第二半导体元件。

2. 发明授权

US08431007B2 Electro-thinning apparatus for removing excess metal from surface metal layer of substrate and removing method using the same 有权
标题翻译：用于从基材的表面金属层除去多余的金属的电镀薄膜装置及使用其的除去方法
公开(公告)号：US08431007B2
公开(公告)日：2013-04-30
申请号：US12625996
申请日：2009-11-25
申请人： Shin-Luh Tarng , Chao-Fu Weng
发明人： Shin-Luh Tarng , Chao-Fu Weng
IPC分类号： C25F3/02 , C25F7/00 , H05K3/07
CPC分类号： C25F7/00 , C25F3/02
摘要： An electro-thinning apparatus for removing excess metal from the surface metal layer of the substrate is provided. The apparatus includes an electrolysis bath, a transportation system, an anode roller, a cathode roller, and at least one shielding plate. The electrolysis bath contains an electrolysis liquid. The transportation system is disposed in the electrolysis bath for moving a substrate from an upstream end to a downstream end. The anode roller is disposed relative to the electrolysis bath and located upstream to the transportation system. The cathode roller is located above the transportation system and located downstream to the anode roller. The at least one shielding plate is located downstream to the cathode roller. During electrolysis, the anode roller contacts a surface metal layer of the substrate while the cathode roller is partly immersed in the electrolysis liquid and away from the surface metal layer of the substrate during electrolysis.
摘要翻译：提供了用于从基板的表面金属层去除多余金属的电薄化装置。该设备包括电解槽，输送系统，阳极辊，阴极辊和至少一个屏蔽板。电解槽含有电解液。输送系统设置在电解槽中，用于将基底从上游端移动到下游端。阳极辊相对于电解槽设置并位于运输系统的上游。阴极辊位于运输系统的上方，位于阳极辊的下游。至少一个屏蔽板位于阴极辊的下游。在电解过程中，阳极辊接触基板的表面金属层，而阴极辊在电解过程中部分地浸入电解液中并远离基板的表面金属层。

3. 发明授权

US07581666B2 Wire-bonding method for wire-bonding apparatus 有权
标题翻译：引线接合装置的接线方法
公开(公告)号：US07581666B2
公开(公告)日：2009-09-01
申请号：US11905868
申请日：2007-10-05
申请人： Ho-Ming Tong , Teck-Chong Lee , Chao-Fu Weng , Chian-Chi Lin , Chih-Nan Wei , Song-Fu Yang , Chia-Jung Tsai , Kao-Ming Su
发明人： Ho-Ming Tong , Teck-Chong Lee , Chao-Fu Weng , Chian-Chi Lin , Chih-Nan Wei , Song-Fu Yang , Chia-Jung Tsai , Kao-Ming Su
IPC分类号： B23K31/12 , B23K20/00 , B23K31/00
CPC分类号： H01L24/93 , B23K20/004 , H01L2224/78901 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , Y10S228/904
摘要： A wire-bonding method for a wire-bonding apparatus is provided. The wire-bonding apparatus includes at least a first wire-bonder and a second wire-bonder for respectively bonding at least several first chips in a first region and several second chips in a second region on a substrate simultaneously. The wire-bonding method includes following steps. First, initial position coordinates of the first region and the second region are obtained. Next, it is determined whether a space between the first region and the second region is greater than a predetermined space. When the space between the first region and the second region is greater than the predetermined space, the first wire-bonder and the second wire-bonder respectively bond the first chips and the second chips simultaneously.
摘要翻译：提供了一种用于引线接合装置的引线接合方法。引线接合装置至少包括第一引线接合器和第二引线接合器，用于分别在基板上的第一区域中的至少几个第一芯片和第二区域中的第二区域中的几个第二芯片。引线键合方法包括以下步骤。首先，获得第一区域和第二区域的初始位置坐标。接下来，确定第一区域和第二区域之间的空间是否大于预定空间。当第一区域和第二区域之间的空间大于预定空间时，第一引线接合器和第二引线接合器分别同时地接合第一芯片和第二芯片。

4. 发明申请

US20080035706A1 Wire-bonding apparatus and wire-bonding method thereof 审中-公开
标题翻译：引线接合装置及其引线接合方法
公开(公告)号：US20080035706A1
公开(公告)日：2008-02-14
申请号：US11646304
申请日：2006-12-28
申请人： Ho-Ming Tong , Kao-Ming Su , Chao-Fu Weng , Teck-Chong Lee , Chian-Chi Lin , Chia-Jung Tsai , Chih-Nan Wei , Song-Fu Yang
发明人： Ho-Ming Tong , Kao-Ming Su , Chao-Fu Weng , Teck-Chong Lee , Chian-Chi Lin , Chia-Jung Tsai , Chih-Nan Wei , Song-Fu Yang
IPC分类号： B23K20/12
CPC分类号： B23K20/005 , H01L2224/78 , H01L2924/14 , H01L2924/1433
摘要： A wire-bonding apparatus is used for wire-bonding at least a first chip and a second chip on a substrate at the same time. The wire-bonding apparatus includes at least a first capillary, a second capillary, a driving unit, a processing unit and a database. The driving unit is used for driving the first capillary and the second capillary. The processing unit is used for outputting a command to the driving unit to control the first capillary and the second capillary. The database is used for storing an operating parameter data. The processing unit controls the first capillary and the second capillary according to the operating parameter data.
摘要翻译：引线接合装置用于同时将至少第一芯片和第二芯片引线接合在基板上。引线接合装置至少包括第一毛细管，第二毛细管，驱动单元，处理单元和数据库。驱动单元用于驱动第一毛细管和第二毛细管。处理单元用于向驱动单元输出命令以控制第一毛细管和第二毛细管。数据库用于存储操作参数数据。处理单元根据操作参数数据控制第一毛细管和第二毛细管。

5. 发明授权

US07015130B2 Method for making UBM pads and bumps on wafer 有权
标题翻译：在晶圆上制造UBM焊盘和凸块的方法
公开(公告)号：US07015130B2
公开(公告)日：2006-03-21
申请号：US10716425
申请日：2003-11-20
申请人： Chi-Long Tsai , Min-Lung Huang , Chao-Fu Weng , En-Chieh Wu , Yang Hong-Zen
发明人： Chi-Long Tsai , Min-Lung Huang , Chao-Fu Weng , En-Chieh Wu , Yang Hong-Zen
IPC分类号： H01L21/44
CPC分类号： H01L24/03 , H01L24/02 , H01L24/11 , H01L24/12 , H01L2224/03912 , H01L2224/0401 , H01L2224/1147 , H01L2224/11472 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/14
摘要： A method for making UBM (Under Bump Metallurgy) pads and bumps on a wafer is disclosed. Openings are formed in a photoresist layer for forming bumps, a positive liquid photoresist is provided into the openings of the photoresist layer for forming bumps. The positive liquid photoresist is exposed and developed to modify the openings of the photoresist layer. Thus, bumps formed in the modified openings have precise bonding areas on the UBM layer. Using the bumps as a mask, UBM pads under the bumps are formed by etching the UBM layer, so that the reflowed bumps have a uniform height.
摘要翻译：公开了一种在晶圆上制造UBM（低爆发冶金）焊盘和凸块的方法。在用于形成凸块的光致抗蚀剂层中形成开口，在用于形成凸块的光致抗蚀剂层的开口中提供正性液体光致抗蚀剂。正极液体光致抗蚀剂被曝光和显影以改变光致抗蚀剂层的开口。因此，在修改后的开口中形成的凸起在UBM层上具有精确的结合区域。使用凸块作为掩模，通过蚀刻UBM层来形成凸块下的UBM焊盘，使得回流的凸块具有均匀的高度。

6. 发明授权

US06861346B2 Solder ball fabricating process 有权
标题翻译：焊球制造工艺
公开(公告)号：US06861346B2
公开(公告)日：2005-03-01
申请号：US10604743
申请日：2003-08-14
申请人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Min-Lung Huang , Jau-Shoung Chen , Ching-Huei Su , Chao-Fu Weng , Yung-Chi Lee , Yu-Chen Chou
发明人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Min-Lung Huang , Jau-Shoung Chen , Ching-Huei Su , Chao-Fu Weng , Yung-Chi Lee , Yu-Chen Chou
IPC分类号： H01L21/60 , H01K21/44 , B23K31/02
CPC分类号： H01L24/11 , H01L2224/0401 , H01L2224/05124 , H01L2224/05139 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05172 , H01L2224/05184 , H01L2224/05558 , H01L2224/05571 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05672 , H01L2224/05684 , H01L2224/11332 , H01L2224/11334 , H01L2224/1147 , H01L2224/11474 , H01L2224/11906 , H01L2224/13099 , H01L2924/0002 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/351 , H01L2924/00 , H01L2224/05552 , H01L2924/00014 , H01L2924/013
摘要： A solder ball fabricating process for forming solder balls over a wafer having an active layer is provided. A patterned solder mask layer is formed over the active surface of the wafer. The patterned solder mask layer has an opening that exposes a bonding pad on the wafer. Solder material is deposited into the opening over the bonding pad. A reflow process is conducted to form a pre-solder body. The aforementioned steps are repeated so that various solder materials are fused together to form a solder ball over the bonding pad.
摘要翻译：提供了一种用于在具有有源层的晶片上形成焊球的焊球制造工艺。在晶片的有效表面上形成图案化的焊接掩模层。图案化的焊接掩模层具有暴露晶片上的焊盘的开口。焊料沉积在焊盘上的开口中。进行回流工艺以形成预焊料体。重复上述步骤，使得各种焊料材料熔合在一起以在焊盘上形成焊球。

7. 发明授权

US06664128B2 Bump fabrication process 有权
标题翻译：凸起制造工艺
公开(公告)号：US06664128B2
公开(公告)日：2003-12-16
申请号：US10248716
申请日：2003-02-12
申请人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Min-Lung Huang , Jau-Shoung Chen , Ching-Huei Su , Chao-Fu Weng , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
发明人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Min-Lung Huang , Jau-Shoung Chen , Ching-Huei Su , Chao-Fu Weng , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
IPC分类号： H01L2144
CPC分类号： C25F3/02 , C23F1/26 , H01L21/32134 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05572 , H01L2224/1147 , H01L2224/131 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H05K3/3473 , H05K2203/054 , H01L2224/13099 , H01L2924/00014
摘要： The present invention provides a bump fabrication process. After forming an under bump metallurgy (UBM) layer and bumps in sequence over the substrate, the under bump metallurgy layer that is not covered by the bumps is etched with an etchant. The etchant mainly comprises sulfuric acid and de-ionized water. The etchant can etch the nickel-vanadium layer of the UBM layer without damaging the bumps.
摘要翻译：本发明提供一种凸块制造工艺。在衬底上顺序地形成凹凸不平的冶金（UBM）层和凸块之后，用蚀刻剂蚀刻未被凸块覆盖的凸块下金属层。蚀刻剂主要包括硫酸和去离子水。蚀刻剂可以蚀刻UBM层的镍钒层，而不会损坏凸块。

8. 发明申请

US20110285006A1 Semiconductor Package and Method for Making the Same 有权
标题翻译：半导体封装及其制作方法
公开(公告)号：US20110285006A1
公开(公告)日：2011-11-24
申请号：US12783104
申请日：2010-05-19
申请人： Chao-Fu Weng , Yi-Ting Wu
发明人： Chao-Fu Weng , Yi-Ting Wu
IPC分类号： H01L23/538 , H01L21/78 , H01L21/50
CPC分类号： H01L23/48 , H01L23/13 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L25/0652 , H01L2224/24227 , H01L2225/06517 , H01L2225/06531 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/014 , H01L2924/15153 , H01L2924/15165
摘要： The present invention relates to a semiconductor package and method for making the same. The semiconductor package includes a silicon substrate unit, a bridge chip and at least one active chip. The silicon substrate unit has a cavity and a plurality of vias. The bridge chip is attached to the cavity and has a plurality of non-contact pads. The active chip is disposed above the bridge chip and has a plurality of non-contact pads and a plurality of conducting elements. The conducting elements of the active chip contact the vias of the silicon substrate unit, the non-contact pads of the active chip face but are not in physical contact with the non-contact pads of the bridge chip, so as to provide proximity communication between the active chip and the bridge chip.
摘要翻译：半导体封装及其制造方法技术领域本发明涉及半导体封装及其制造方法。半导体封装包括硅衬底单元，桥芯片和至少一个有源芯片。硅衬底单元具有空腔和多个通孔。桥芯片附接到腔体并具有多个非接触垫片。有源芯片设置在桥芯片上方并且具有多个非接触焊盘和多个导电元件。有源芯片的导电元件接触硅衬底单元的通孔，有源芯片面的非接触焊盘，但不与桥芯片的非接触焊盘物理接触，以便提供有源芯片和桥芯片。

9. 发明申请

US20060017171A1 Formation method and structure of conductive bumps 审中-公开
标题翻译：导电凸块的形成方法和结构
公开(公告)号：US20060017171A1
公开(公告)日：2006-01-26
申请号：US11185848
申请日：2005-07-21
申请人： Chao-Fu Weng
发明人： Chao-Fu Weng
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/13099 , H01L2224/131 , H01L2924/00013 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01042 , H01L2924/01045 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/00014
摘要： A formation method and structure of conductive bump are provided. A conductive bump is formed on a wafer through an under bump metallurgy layer. A nickel-based wetting layer in the under bump metallurgy layer is applied on the conductive bump to prevent stannum in the conductive bump from diffusing downwards.
摘要翻译：提供导电凸块的形成方法和结构。通过下凸块冶金层在晶片上形成导电凸块。在凸块状金属层上的镍基润湿层被施加在导电凸块上以防止导电凸块中的锡向下扩散。

10. 发明授权

US06877653B2 Method of modifying tin to lead ratio in tin-lead bump 有权
标题翻译：锡铅凸点中锡与铅比的修改方法
公开(公告)号：US06877653B2
公开(公告)日：2005-04-12
申请号：US10248411
申请日：2003-01-17
申请人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Min-Lung Huang , Jau-Shoung Chen , Ching-Huei Su , Chao-Fu Weng , Yung-Chi Lee , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
发明人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Min-Lung Huang , Jau-Shoung Chen , Ching-Huei Su , Chao-Fu Weng , Yung-Chi Lee , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
IPC分类号： B23K35/02 , B23K35/26 , H05K3/34 , B23K31/02 , B23K31/00 , B23K35/24
CPC分类号： H05K3/3484 , B23K35/0244 , B23K35/025 , B23K35/262 , B23K35/268 , H05K3/3463 , H05K2201/0379 , H05K2203/043 , H05K2203/0568
摘要： A method of modifying the tin to lead ratio of a tin-lead bump forms a patterned solder mask over a substrate that comprises a first tin-lead bump formed thereon, the patterned solder mask having an opening that exposes the tin-lead bump. A solder material including tin and lead is filled in the opening of the solder mask over the first tin-lead bump. The solder material has a tin to lead ratio that differs from that of the first tin-lead bump. The solder material is reflowed to fuse with the first tin-lead bump, which forms a second tin-lead bump. The tin to lead ratio of the second tin-lead bump is thereby different from that of the first tin-lead bump.
摘要翻译：改变锡铅凸块的锡引导比的方法在衬底上形成图案化的焊料掩模，该衬底包括形成在其上的第一锡铅凸块，所述图案化焊料掩模具有暴露锡铅凸块的开口。包括锡和铅的焊料材料填充在第一锡铅凸块上的焊料掩模的开口中。焊锡材料具有与第一锡铅凸块不同的锡与引线比。焊料材料被回流以与形成第二锡铅凸块的第一锡铅凸块熔合。因此，第二锡铅凸块的锡与引线比不同于第一锡铅凸块的锡引导比。

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