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1. 发明授权

US06437411B1 Semiconductor device having chamfered silicide layer and method for manufacturing the same 失效
标题翻译：具有倒角硅化物层的半导体器件及其制造方法
公开(公告)号：US06437411B1
公开(公告)日：2002-08-20
申请号：US09536427
申请日：2000-03-27
申请人： Chang-won Choi , Dae-hyuk Chung , Woo-sik Kim , Shin-woo Nam , Yeo-cheol Yoon , Bum-su Kim , Jong-ho Park , Ji-hwan Choi
发明人： Chang-won Choi , Dae-hyuk Chung , Woo-sik Kim , Shin-woo Nam , Yeo-cheol Yoon , Bum-su Kim , Jong-ho Park , Ji-hwan Choi
IPC分类号： H01L2976
CPC分类号： H01L21/02071 , H01L21/28114 , H01L21/32134 , H01L21/32137 , H01L21/76897 , H01L23/5258 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a chamfered silicide layer and a manufacturing method of the same. The semiconductor device includes: a first insulation layer overlying a semiconductor substrate; gate structures including first conductive layer patterns formed on the first insulation layer, and second conductive layer patterns which are formed on the first conductive layer patterns, wherein the lower sides of the second conductive layer patterns are substantially perpendicular to the major surface of the semiconductor substrate and the upper sides of the second conductive layer patterns are chamfered; and a second insulation layer formed with a first width W on the second conductive layer patterns, wherein the sidewalls of the second insulation layer overhang the upper edges of the second conductive layer patterns. In the semiconductor device manufacture, in forming undercut regions which define the chamfered upper edges of the metal silicide layer patterns, isotropic dry etching is carried out, wherein the isotropic dry etching can be performed simultaneously with ashing of photoresist patterns, or immediately after the ashing process in the same chamber. In either case, after the ashing of the photoresist patterns, an isotropic wet etching can be carried out immediately after performing an existing stripping process, so as to form the undercut regions.
摘要翻译：具有倒角硅化物层的半导体器件及其制造方法。半导体器件包括：覆盖半导体衬底的第一绝缘层; 包括形成在第一绝缘层上的第一导电层图案的栅结构和形成在第一导电层图案上的第二导电层图案，其中第二导电层图案的下侧基本垂直于半导体衬底的主表面并且第二导电层图案的上侧被倒角; 以及在第二导电层图案上形成有第一宽度W的第二绝缘层，其中第二绝缘层的侧壁悬垂在第二导电层图案的上边缘上。在半导体器件制造中，在形成限定金属硅化物层图案的倒角上边缘的底切区域时，进行各向同性干蚀刻，其中各向同性干蚀刻可以与光致抗蚀剂图案的灰化或灰化之后立即同时进行过程在同一个房间。在任一种情况下，在光致抗蚀剂图案的灰化之后，可以在执行现有的剥离工艺之后立即进行各向同性的湿蚀刻，以形成底切区域。

2. 发明授权

US06740550B2 Methods of manufacturing semiconductor devices having chamfered silicide layers therein 失效
标题翻译：制造其中具有倒角的硅化物层的半导体器件的方法
公开(公告)号：US06740550B2
公开(公告)日：2004-05-25
申请号：US10190086
申请日：2002-07-03
申请人： Chang-won Choi , Dae-hyuk Chung , Woo-sik Kim , Shin-woo Nam , Yeo-cheol Yoon , Bum-su Kim , Jong-ho Park , Ji-hwan Choi
发明人： Chang-won Choi , Dae-hyuk Chung , Woo-sik Kim , Shin-woo Nam , Yeo-cheol Yoon , Bum-su Kim , Jong-ho Park , Ji-hwan Choi
IPC分类号： H01L218238
CPC分类号： H01L21/02071 , H01L21/28114 , H01L21/32134 , H01L21/32137 , H01L21/76897 , H01L23/5258 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a chamfered silicide layer and a manufacturing method of the same. The semiconductor device includes: a first insulation layer overlying a semiconductor substrate; gate structures including first conductive layer patterns formed on the first insulation layer, and second conductive layer patterns which are formed on the first conductive layer patterns, wherein the lower sides of the second conductive layer patterns are substantially perpendicular to the major surface of the semiconductor substrate and the upper sides of the second conductive layer patterns are chamfered; and a second insulation layer formed with a first width W on the second conductive layer patterns, wherein the sidewalls of the second insulation layer overhang the upper edges of the second conductive layer patterns. In the semiconductor device manufacture, in forming undercut regions which define the chamfered upper edges of the metal silicide layer patterns, isotropic dry etching is carried out, wherein the isotropic dry etching can be performed simultaneously with ashing of photoresist patterns, or immediately after the ashing process in the same chamber. In either case, after the ashing of the photoresist patterns, an isotropic wet etching can be carried out immediately after performing an existing stripping process, so as to form the undercut regions.
摘要翻译：具有倒角硅化物层的半导体器件及其制造方法。半导体器件包括：覆盖半导体衬底的第一绝缘层; 包括形成在第一绝缘层上的第一导电层图案的栅结构和形成在第一导电层图案上的第二导电层图案，其中第二导电层图案的下侧基本垂直于半导体衬底的主表面并且第二导电层图案的上侧被倒角; 以及在第二导电层图案上形成有第一宽度W的第二绝缘层，其中第二绝缘层的侧壁悬垂在第二导电层图案的上边缘上。在半导体器件制造中，在形成限定金属硅化物层图案的倒角上边缘的底切区域时，进行各向同性干蚀刻，其中各向同性干蚀刻可以与光致抗蚀剂图案的灰化或灰化之后立即同时进行过程在同一个房间。在任一种情况下，在光致抗蚀剂图案的灰化之后，可以在执行现有的剥离工艺之后立即执行各向同性的湿蚀刻，以形成底切区域。

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