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1. 发明授权

US08455871B2 Thin film transistor array panel and method for manufacturing the same 有权
公开(公告)号：US08455871B2
公开(公告)日：2013-06-04
申请号：US12859792
申请日：2010-08-20
申请人： Chang-Oh Jeong , Woo-Sung Sohn , Dong-Gyu Kim , Shi-Yul Kim , Ki-Yeup Lee , Jean-Ho Song
发明人： Chang-Oh Jeong , Woo-Sung Sohn , Dong-Gyu Kim , Shi-Yul Kim , Ki-Yeup Lee , Jean-Ho Song
IPC分类号： H01L29/04
CPC分类号： H01L33/16 , H01L27/124 , H01L27/1288
摘要： A thin film transistor array panel is provided and includes a gate line, a gate insulating layer covering the gate line, a semiconductor layer disposed on the gate insulating layer, and a data line and a drain electrode disposed on the semiconductor layer. The data line and the drain electrode have a dual-layered structure including a lower layer and an upper layer with the lower layer having a first portion protruded outside the upper layer and the semiconductor layer having a second portion protruded outside the edge of the lower layer.

2. 发明授权

US08865528B2 Thin film transistor substrate and the method thereof 有权
标题翻译：薄膜晶体管基板及其制造方法
公开(公告)号：US08865528B2
公开(公告)日：2014-10-21
申请号：US12844356
申请日：2010-07-27
申请人： Jean-Ho Song , Shin-Il Choi , Sun-Young Hong , Shi-Yul Kim , Ki-Yeup Lee , Jae-Hyoung Youn , Sung-Ryul Kim , O-Sung Seo , Yang-Ho Bae , Jong-Hyun Choung , Dong-Ju Yang , Bong-Kyun Kim , Hwa-Yeul Oh , Pil-Soon Hong , Byeong-Beom Kim , Je-Hyeong Park , Yu-Gwang Jeong , Jong-In Kim , Nam-Seok Suh
发明人： Jean-Ho Song , Shin-Il Choi , Sun-Young Hong , Shi-Yul Kim , Ki-Yeup Lee , Jae-Hyoung Youn , Sung-Ryul Kim , O-Sung Seo , Yang-Ho Bae , Jong-Hyun Choung , Dong-Ju Yang , Bong-Kyun Kim , Hwa-Yeul Oh , Pil-Soon Hong , Byeong-Beom Kim , Je-Hyeong Park , Yu-Gwang Jeong , Jong-In Kim , Nam-Seok Suh
IPC分类号： H01L21/84 , H01L27/12
CPC分类号： H01L27/124 , H01L27/12 , H01L27/1214 , H01L27/1288 , H01L29/42368 , H01L29/458 , H01L29/78669
摘要： A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
摘要翻译：薄膜晶体管阵列面板包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的数据线和漏极，钝化层覆盖数据线和漏电极，并且具有露出漏电极的一部分的接触孔，以及通过接触孔与漏电极电连接的像素电极。数据线和漏极各自具有包括钛的下层和铜的上层的双层，下层比上层宽，下层具有暴露的区域。栅极绝缘层可以具有台阶形状。

3. 发明授权

US08476123B2 Method for manufacturing thin film transistor array panel 有权
标题翻译：制造薄膜晶体管阵列面板的方法
公开(公告)号：US08476123B2
公开(公告)日：2013-07-02
申请号：US13109686
申请日：2011-05-17
申请人： Dong-Ju Yang , Yu-Gwang Jeong , Jean-Ho Song , Ki-Yeup Lee , Shin-Il Choi , Tae-Woo Kim
发明人： Dong-Ju Yang , Yu-Gwang Jeong , Jean-Ho Song , Ki-Yeup Lee , Shin-Il Choi , Tae-Woo Kim
IPC分类号： H01L21/84
CPC分类号： H01L27/1288 , H01L21/32138 , H01L27/1214 , H01L27/1255 , H01L29/458
摘要： A method for manufacturing a thin film transistor array panel includes forming a gate line; forming an insulating layer on the gate line; forming first and second silicon layers first and second metal layers; forming a photoresist pattern having first and second portions; forming first and second metal patterns by etching the first and second metal layers; processing the first metal pattern with SF6 or SF6/He; forming silicon and semiconductor patterns by etching the second and first silicon layers; removing the first portion of the photoresist pattern; forming an upper layer of a data wire by wet etching the second metal pattern; forming a lower layer of the data wire and an ohmic contact by etching the first metal and amorphous silicon patterns; forming a passivation layer including a contact hole on the upper layer; and forming a pixel electrode on the passivation layer.
摘要翻译：薄膜晶体管阵列板的制造方法包括：形成栅极线; 在栅极线上形成绝缘层; 第一和第二硅层第一和第二金属层; 形成具有第一和第二部分的光致抗蚀剂图案; 通过蚀刻第一和第二金属层来形成第一和第二金属图案; 用SF6或SF6 / He处理第一金属图案; 通过蚀刻第二和第一硅层形成硅和半导体图案; 去除光致抗蚀剂图案的第一部分; 通过湿法蚀刻第二金属图案形成数据线的上层; 通过蚀刻第一金属和非晶硅图案形成数据线的下层和欧姆接触; 在上层形成包括接触孔的钝化层; 以及在所述钝化层上形成像素电极。

4. 发明申请

US20120064678A1 MANUFACTURING METHOD OF THIN FILM TRANSISTOR ARRAY PANEL 审中-公开
标题翻译：薄膜晶体管阵列的制造方法
公开(公告)号：US20120064678A1
公开(公告)日：2012-03-15
申请号：US13069070
申请日：2011-03-22
申请人： Byeong-Jin LEE , Yu-Gwang Jeong , Dong-Ju Yang , Bong-Kyun Kim , Hong-Sick Park , Byeong-Beom Kim , Sang-Gab Kim , Ji-Young Park , Jean-Ho Song , Ki-Yeup Lee , Shin-Il Choi
发明人： Byeong-Jin LEE , Yu-Gwang Jeong , Dong-Ju Yang , Bong-Kyun Kim , Hong-Sick Park , Byeong-Beom Kim , Sang-Gab Kim , Ji-Young Park , Jean-Ho Song , Ki-Yeup Lee , Shin-Il Choi
IPC分类号： H01L21/336
CPC分类号： H01L27/1288 , H01L27/1214 , H01L29/458 , H01L29/4908 , H01L29/66765 , H01L29/78678
摘要： A method for manufacturing a TFT array panel includes forming a photosensitive film pattern with first and second parts in first and second sections on a metal layer, etching the metal layer of a third section using the film pattern as a mask to form first and second metal patterns, etching the film pattern to remove the first part, etching first and second amorphous silicon layers of the third section using the second part as a mask to form an amorphous silicon pattern and a semiconductor, etching the first and second metal patterns of the first section using the second part as a mask to form a source electrode and a drain electrode including an upper layer and a lower layer, and etching the amorphous silicon pattern of the region corresponding to the first section by using the second part as a mask to form an ohmic contact.
摘要翻译：一种TFT阵列板的制造方法，其特征在于，在金属层的第一和第二部分中形成具有第一和第二部分的感光膜图案，使用所述膜图案作为掩模蚀刻第三部分的金属层，以形成第一和第二金属蚀刻薄膜图案以去除第一部分，使用第二部分作为掩模蚀刻第三部分的第一和第二非晶硅层以形成非晶硅图案和半导体，蚀刻第一部分的第一和第二金属图案使用第二部分作为掩模形成源电极和包括上层和下层的漏极，并且通过使用第二部分作为掩模来蚀刻与第一部分相对应的区域的非晶硅图案以形成欧姆接触。

5. 发明授权

US08450737B2 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US08450737B2
公开(公告)日：2013-05-28
申请号：US12784376
申请日：2010-05-20
申请人： Shin-Il Choi , Yu-Gwang Jeong , Ki-Yeup Lee , Dong-Ju Yang , Jean-Ho Song
发明人： Shin-Il Choi , Yu-Gwang Jeong , Ki-Yeup Lee , Dong-Ju Yang , Jean-Ho Song
IPC分类号： H01L31/00
CPC分类号： H01L27/124 , H01L27/1248 , H01L27/1288
摘要： A thin film transistor array panel includes: a substrate; a signal line disposed on the substrate and including copper (Cu); a passivation layer disposed on the signal line and having a contact hole exposing a portion of the signal line; and a conductive layer disposed on the passivation layer and connected to the portion of the signal line through the contact hole, wherein the passivation layer includes an organic passivation layer including an organic insulator that does not include sulfur, and a method of manufacturing the thin film transistor prevents formation of foreign particles on the signal line.
摘要翻译：薄膜晶体管阵列面板包括：基板; 设置在基板上并包括铜（Cu）的信号线; 钝化层，设置在所述信号线上并具有暴露所述信号线的一部分的接触孔; 以及设置在所述钝化层上并通过所述接触孔连接到所述信号线的所述部分的导电层，其中所述钝化层包括包含不包含硫的有机绝缘体的有机钝化层，以及制造所述薄膜的方法晶体管防止在信号线上形成异物。

6. 发明申请

US20110089421A1 THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20110089421A1
公开(公告)日：2011-04-21
申请号：US12784376
申请日：2010-05-20
申请人： Shin-Il CHOI , Yu-Gwang Jeong , Ki-Yeup Lee , Dong-Ju Yang , Jean-Ho Song
发明人： Shin-Il CHOI , Yu-Gwang Jeong , Ki-Yeup Lee , Dong-Ju Yang , Jean-Ho Song
IPC分类号： H01L29/786 , H01L27/12 , H01L21/782
CPC分类号： H01L27/124 , H01L27/1248 , H01L27/1288
摘要： A thin film transistor array panel includes: a substrate; a signal line disposed on the substrate and including copper (Cu); a passivation layer disposed on the signal line and having a contact hole exposing a portion of the signal line; and a conductive layer disposed on the passivation layer and connected to the portion of the signal line through the contact hole, wherein the passivation layer includes an organic passivation layer including an organic insulator that does not include sulfur, and a method of manufacturing the thin film transistor prevents formation of foreign particles on the signal line.
摘要翻译：薄膜晶体管阵列面板包括：基板; 设置在基板上并包括铜（Cu）的信号线; 钝化层，设置在所述信号线上并具有暴露所述信号线的一部分的接触孔; 以及设置在所述钝化层上并通过所述接触孔连接到所述信号线的所述部分的导电层，其中所述钝化层包括包含不包含硫的有机绝缘体的有机钝化层，以及制造所述薄膜的方法晶体管防止在信号线上形成异物。

7. 发明授权

US08218110B2 Thin film transistor array panel and method of manufacturing the same 失效
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US08218110B2
公开(公告)日：2012-07-10
申请号：US12434945
申请日：2009-05-04
申请人： Jean-Ho Song , Yang-Ho Jung , Hoon Kang , Jae-Sung Kim , Jae-Hyoung Youn , Jong-In Kim , Sang-Soo Kim , Shi-Yul Kim
发明人： Jean-Ho Song , Yang-Ho Jung , Hoon Kang , Jae-Sung Kim , Jae-Hyoung Youn , Jong-In Kim , Sang-Soo Kim , Shi-Yul Kim
IPC分类号： G02F1/1335
CPC分类号： G02F1/136209 , B41J2202/09 , G02F1/133555 , G02F1/133707 , G02F1/13624 , G02F1/136286 , G02F2001/134345 , G02F2001/136222 , G02F2001/136231 , H01L27/1248 , H01L27/1262 , H01L29/41733
摘要： After increasing the thickness of a gate line and forming a barrier rib that is made of an organic material, a gate insulating layer is formed and then a color filter is formed with an Inkjet method using the barrier rib. By increasing a thickness of the gate line, even if the size of a substrate increases, problems due to signal delay are reduced, and by forming a barrier rib with an organic material, the height of the barrier rib increases, and a taper angle increases and thus a color filter is stably formed.
摘要翻译：在增加栅极线的厚度并形成由有机材料制成的阻挡肋之后，形成栅极绝缘层，然后利用使用隔壁的喷墨法形成滤色器。通过增加栅极线的厚度，即使基板的尺寸增加，由于信号延迟引起的问题减少，并且通过用有机材料形成隔壁，障壁的高度增加，并且锥角增加从而稳定地形成滤色器。

8. 发明授权

US06905917B2 Thin film transistor array panel for liquid crystal display and method for manufacturing the same 有权
公开(公告)号：US06905917B2
公开(公告)日：2005-06-14
申请号：US10112890
申请日：2002-04-01
申请人： Jean-Ho Song , Chang-Oh Jeong
发明人： Jean-Ho Song , Chang-Oh Jeong
IPC分类号： G02F1/1368 , G02F1/136 , G02F1/1362 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L29/786 , H01L29/74
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/13629
摘要： A method of fabricating a thin film transistor array panel for a liquid crystal display is provided. A gate line assembly is formed on an insulating substrate. The gate line assembly includes gate lines and gate electrodes connected to the gate lines. A gate insulating layer is formed on the insulating substrate having the gate line assembly. A semiconductor layer is formed on the gate insulating layer. A data line assembly is formed, the data line assembly includes data lines crossing over the gate lines, source electrodes connected to the data lines and placed adjacent to the gate electrodes, and drain electrodes placed opposite to the source electrodes with respect to the gate electrodes. A protective layer is deposited onto the insulating substrate having the data line assembly. The protective layer is patterned to form first contact holes exposing the drain electrodes. Pixel electrodes are formed on the protective layer such that the pixel electrodes are electrically connected to the drain electrodes, wherein one of the gate line assembly and the data line assembly further includes a low resistance conductive layer.

9. 发明授权

US07599037B2 Thin film transistor array panel for liquid crystal display and method for manufacturing the same 有权
标题翻译：用于液晶显示器的薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07599037B2
公开(公告)日：2009-10-06
申请号：US10895866
申请日：2004-07-21
申请人： Jean-Ho Song , Chang-Oh Jeong
发明人： Jean-Ho Song , Chang-Oh Jeong
IPC分类号： G02F1/1343
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/13629
摘要： A method of fabricating a thin film transistor array panel for a liquid crystal display is provided. A gate line assembly is formed on an insulating substrate. The gate line assembly includes gate lines and gate electrodes connected to the gate lines. A gate insulating layer is formed on the insulating substrate having the gate line assembly. A semiconductor layer is formed on the gate insulating layer. A data line assembly is formed, the data line assembly includes data lines crossing over the gate lines, source electrodes connected to the data lines and placed adjacent to the gate electrodes, and drain electrodes placed opposite to the source electrodes with respect to the gate electrodes. A protective layer is deposited onto the insulating substrate having the data line assembly. The protective layer is patterned to form first contact holes exposing the drain electrodes. Pixel electrodes are formed on the protective layer such that the pixel electrodes are electrically connected to the drain electrodes, wherein one of the gate line assembly and the data line assembly further includes a low resistance conductive layer.
摘要翻译：提供一种制造用于液晶显示器的薄膜晶体管阵列面板的方法。栅极线组件形成在绝缘基板上。栅极线组件包括连接到栅极线的栅极线和栅电极。在具有栅极线组件的绝缘基板上形成栅极绝缘层。在栅极绝缘层上形成半导体层。形成数据线组件，数据线组件包括跨越栅极线的数据线，连接到数据线并与栅电极相邻放置的源电极，以及相对于栅电极与源电极相对放置的漏电极。保护层沉积在具有数据线组件的绝缘基板上。图案化保护层以形成露出漏电极的第一接触孔。像素电极形成在保护层上，使得像素电极电连接到漏电极，其中栅极线组件和数据线组件中的一个还包括低电阻导电层。

10. 发明申请

US20050041187A1 Thin film transistor array panel for liquid crystal display and method for manufacturing the same 有权
标题翻译：用于液晶显示器的薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20050041187A1
公开(公告)日：2005-02-24
申请号：US10895866
申请日：2004-07-21
申请人： Jean-Ho Song , Chang-Oh Jeong
发明人： Jean-Ho Song , Chang-Oh Jeong
IPC分类号： G02F1/1368 , G02F1/136 , G02F1/1362 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L29/786 , G02F1/1343
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/13629
摘要： A method of fabricating a thin film transistor array panel for a liquid crystal display is provided. A gate line assembly is formed on an insulating substrate. The gate line assembly includes gate lines and gate electrodes connected to the gate lines. A gate insulating layer is formed on the insulating substrate having the gate line assembly. A semiconductor layer is formed on the gate insulating layer. A data line assembly is formed, the data line assembly includes data lines crossing over the gate lines, source electrodes connected to the data lines and placed adjacent to the gate electrodes, and drain electrodes placed opposite to the source electrodes with respect to the gate electrodes. A protective layer is deposited onto the insulating substrate having the data line assembly. The protective layer is patterned to form first contact holes exposing the drain electrodes. Pixel electrodes are formed on the protective layer such that the pixel electrodes are electrically connected to the drain electrodes, wherein one of the gate line assembly and the data line assembly further includes a low resistance conductive layer.
摘要翻译：提供一种制造用于液晶显示器的薄膜晶体管阵列面板的方法。栅极线组件形成在绝缘基板上。栅极线组件包括连接到栅极线的栅极线和栅电极。在具有栅极线组件的绝缘基板上形成栅极绝缘层。在栅极绝缘层上形成半导体层。形成数据线组件，数据线组件包括跨越栅极线的数据线，连接到数据线并与栅电极相邻放置的源电极，以及相对于栅电极与源电极相对放置的漏电极。保护层沉积在具有数据线组件的绝缘基板上。图案化保护层以形成露出漏电极的第一接触孔。像素电极形成在保护层上，使得像素电极电连接到漏电极，其中栅极线组件和数据线组件中的一个还包括低电阻导电层。

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