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1. 发明授权

US07566924B2 Semiconductor device with gate spacer of positive slope and fabrication method thereof 有权
标题翻译：具有正斜率栅极间隔物的半导体器件及其制造方法
公开(公告)号：US07566924B2
公开(公告)日：2009-07-28
申请号：US11249096
申请日：2005-10-11
申请人： Chang-Huhn Lee , Mun-Mo Jeong , Wook-je Kim
发明人： Chang-Huhn Lee , Mun-Mo Jeong , Wook-je Kim
IPC分类号： H01L31/112
CPC分类号： H01L29/6656 , H01L21/823468 , Y10S257/90 , Y10S438/978
摘要： Embodiments of the invention provide a semiconductor device and a fabrication method for a semiconductor device that includes the processes of forming multiple gates on a silicon substrate, forming a gate spacer having a positive slope at the gate spacer edge, depositing a polysilicon layer on the silicon substrate between the gates, etching a portion of the polysilicon layer to form an opening exposing a portion of the silicon substrate, and forming an inter-insulation layer to the exposed portion of the silicon substrate to fill the opening. Using an annealing process applied to a layer in the gate spacer, the etch selectivity can be selectively controlled and consequently, the degree of slope at the gate spacer edge is predetermined.
摘要翻译：本发明的实施例提供一种用于半导体器件的半导体器件和制造方法，其包括在硅衬底上形成多个栅极的工艺，在栅极间隔物边缘处形成具有正斜率的栅极间隔物，在硅上沉积多晶硅层蚀刻多晶硅层的一部分以形成露出硅衬底的一部分的开口，以及形成绝缘层到硅衬底的暴露部分以填充开口。使用施加到栅极间隔物中的层的退火工艺，可以选择性地控制蚀刻选择性，因此预定栅极间隔物边缘处的斜率。

2. 发明申请

US20060027875A1 Semiconductor device with gate space of positive slope and fabrication method thereof 有权
标题翻译：具有正斜率栅极空间的半导体器件及其制造方法
公开(公告)号：US20060027875A1
公开(公告)日：2006-02-09
申请号：US11249096
申请日：2005-10-11
申请人： Chang-Huhn Lee , Mun-Mo Jeong , Wook-je Kim
发明人： Chang-Huhn Lee , Mun-Mo Jeong , Wook-je Kim
IPC分类号： H01L29/94 , H01L29/76 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/6656 , H01L21/823468 , Y10S257/90 , Y10S438/978
摘要： Embodiments of the invention provide a semiconductor device and a fabrication method for a semiconductor device that includes the processes of forming multiple gates on a silicon substrate, forming a gate spacer having a positive slope at the gate spacer edge, depositing a polysilicon layer on the silicon substrate between the gates, etching a portion of the polysilicon layer to form an opening exposing a portion of the silicon substrate, and forming an inter-insulation layer to the exposed portion of the silicon substrate to fill the opening. Using an annealing process applied to a layer in the gate spacer, the etch selectivity can be selectively controlled and consequently, the degree of slope at the gate spacer edge is predetermined.
摘要翻译：本发明的实施例提供一种用于半导体器件的半导体器件和制造方法，其包括在硅衬底上形成多个栅极的工艺，在栅极间隔物边缘处形成具有正斜率的栅极间隔物，在硅上沉积多晶硅层蚀刻多晶硅层的一部分以形成露出硅衬底的一部分的开口，以及形成绝缘层到硅衬底的暴露部分以填充开口。使用施加到栅极间隔物中的层的退火工艺，可以选择性地控制蚀刻选择性，因此预定栅极间隔物边缘处的斜率。

3. 发明授权

US06969673B2 Semiconductor device with gate space of positive slope and fabrication method thereof 有权
标题翻译：具有正斜率栅极空间的半导体器件及其制造方法
公开(公告)号：US06969673B2
公开(公告)日：2005-11-29
申请号：US10631456
申请日：2003-07-30
申请人： Chang-Huhn Lee , Mun-Mo Jeong , Wook-je Kim
发明人： Chang-Huhn Lee , Mun-Mo Jeong , Wook-je Kim
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/3205
CPC分类号： H01L29/6656 , H01L21/823468 , Y10S257/90 , Y10S438/978
摘要： Embodiments of the invention provide a semiconductor device and a fabrication method for a semiconductor device that includes the processes of forming multiple gates on a silicon substrate, forming a gate spacer having a positive slope at the gate spacer edge, depositing a polysilicon layer on the silicon substrate between the gates, etching a portion of the polysilicon layer to form an opening exposing a portion of the silicon substrate, and forming an inter-insulation layer to the exposed portion of the silicon substrate to fill the opening. Using an annealing process applied to a layer in the gate spacer, the etch selectivity can be selectively controlled and consequently, the degree of slope at the gate spacer edge is predetermined.
摘要翻译：本发明的实施例提供一种用于半导体器件的半导体器件和制造方法，其包括在硅衬底上形成多个栅极的工艺，在栅极间隔物边缘处形成具有正斜率的栅极间隔物，在硅上沉积多晶硅层蚀刻多晶硅层的一部分以形成露出硅衬底的一部分的开口，以及形成绝缘层到硅衬底的暴露部分以填充开口。使用施加到栅极间隔物中的层的退火工艺，可以选择性地控制蚀刻选择性，因此预定栅极间隔物边缘处的斜率。

4. 发明授权

US07473954B2 Bitline of semiconductor device having stud type capping layer and method for fabricating the same 有权
标题翻译：具有螺柱型盖层的半导体器件的位线及其制造方法
公开(公告)号：US07473954B2
公开(公告)日：2009-01-06
申请号：US11249097
申请日：2005-10-11
申请人： Mun-Mo Jeong , Chang-Huhn Lee , Makoto Yoshida
发明人： Mun-Mo Jeong , Chang-Huhn Lee , Makoto Yoshida
IPC分类号： H01L29/94
CPC分类号： H01L27/10855 , H01L27/10814 , H01L27/10885
摘要： A semiconductor device with a bitline structure has a stud type capping layer. A method of fabricating the same achieves sufficient process margins and reduces parasitic capacitance.The device may include an insulating film formed on a semiconductor substrate and having a bitline contact and a groove-shaped bitline pattern, a bitline formed on the bitline contact and on a portion of the bitline pattern and that is surrounded by the insulating film, and a bitline capping layer formed on the bitline within the bitline pattern and the insulating film that protrudes from the insulating film. A protruded portion of the bitline capping layer is wider than a width of the bitline.
摘要翻译：具有位线结构的半导体器件具有螺柱型封盖层。其制造方法实现了足够的工艺裕度并降低了寄生电容。该器件可以包括形成在半导体衬底上并且具有位线接触和凹槽形位线图案的绝缘膜，形成在位线接触上的位线和位线图案的一部分并被绝缘膜包围的位线，以及在位线图案内的位线上形成的位线封盖层和从绝缘膜突出的绝缘膜。位线封盖层的突出部分宽于位线的宽度。

5. 发明授权

US07217618B2 Semiconductor device and method for fabricating the same using damascene process 失效
标题翻译：半导体装置及其制造方法，使用镶嵌工艺
公开(公告)号：US07217618B2
公开(公告)日：2007-05-15
申请号：US10678530
申请日：2003-10-03
申请人： Chang-Huhn Lee , Mun-Mo Jeong
发明人： Chang-Huhn Lee , Mun-Mo Jeong
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L21/31116 , H01L27/10814 , H01L27/10852 , H01L27/10855 , H01L27/10885
摘要： A semiconductor device and method for fabricating same according to an embodiment of the invention includes: preparing a semiconductor substrate having a first contact pad and a second contact pad; forming a first insulating film on the substrate; etching the first insulating film to form a groove-shaped bit line pattern and a contact exposing the first contact pad and the second contact pad, respectively; simultaneously forming a contact plug and a bit line in the contact and the bit line pattern, respectively, the contact plug and the bitline having upper surfaces that are coplanar; and forming a bottom electrode for a capacitor that is connected to the first contact pad.
摘要翻译：根据本发明实施例的半导体器件及其制造方法包括：制备具有第一接触焊盘和第二接触焊盘的半导体衬底; 在所述基板上形成第一绝缘膜; 蚀刻第一绝缘膜以形成槽状位线图案和分别暴露第一接触焊盘和第二接触焊盘的接触; 同时分别在触点和位线图案中形成接触插塞和位线，接触插塞和具有共面的上表面的位线; 以及形成用于连接到第一接触焊盘的电容器的底部电极。

6. 发明申请

US20060027852A1 Bitline of semiconductor device having stud type capping layer and method for fabricating the same 有权
公开(公告)号：US20060027852A1
公开(公告)日：2006-02-09
申请号：US11249097
申请日：2005-10-11
申请人： Mun-Mo Jeong , Chang-Huhn Lee , Makoto Yoshida
发明人： Mun-Mo Jeong , Chang-Huhn Lee , Makoto Yoshida
IPC分类号： H01L29/94 , H01L29/00
CPC分类号： H01L27/10855 , H01L27/10814 , H01L27/10885
摘要： A semiconductor device with a bitline structure has a stud type capping layer. A method of fabricating the same achieves sufficient process margins and reduces parasitic capacitance. The device may include an insulating film formed on a semiconductor substrate and having a bitline contact and a groove-shaped bitline pattern, a bitline formed on the bitline contact and on a portion of the bitline pattern and that is surrounded by the insulating film, and a bitline capping layer formed on the bitline within the bitline pattern and the insulating film that protrudes from the insulating film. A protruded portion of the bitline capping layer is wider than a width of the bitline.

7. 发明授权

US06982199B2 Bitline of semiconductor device having stud type capping layer and method for fabricating the same 有权
标题翻译：具有螺柱型盖层的半导体器件的位线及其制造方法
公开(公告)号：US06982199B2
公开(公告)日：2006-01-03
申请号：US10636131
申请日：2003-08-06
申请人： Mun-Mo Jeong , Chang-Huhn Lee , Makoto Yoshida
发明人： Mun-Mo Jeong , Chang-Huhn Lee , Makoto Yoshida
IPC分类号： H01L21/8242
CPC分类号： H01L27/10855 , H01L27/10814 , H01L27/10885
摘要： A semiconductor device with a bitline structure has a stud type capping layer. A method of fabricating the same achieves sufficient process margins and reduces parasitic capacitance. The device may include an insulating film formed on a semiconductor substrate and having a bitline contact and a groove-shaped bitline pattern, a bitline formed on the bitline contact and on a portion of the bitline pattern and that is surrounded by the insulating film, and a bitline capping layer formed on the bitline within the bitline pattern and the insulating film that protrudes from the insulating film. A protruded portion of the bitline capping layer is wider than the width of the bitline.
摘要翻译：具有位线结构的半导体器件具有螺柱型封盖层。其制造方法实现了足够的工艺裕度并降低了寄生电容。该器件可以包括形成在半导体衬底上并且具有位线接触和凹槽形位线图案的绝缘膜，形成在位线接触上的位线和位线图案的一部分并被绝缘膜包围的位线，以及在位线图案内的位线上形成的位线封盖层和从绝缘膜突出的绝缘膜。位线封盖层的突出部分比位线的宽度宽。

8. 发明授权

US07132362B2 Semiconductor device with contacts having uniform contact resistance and method for manufacturing the same 失效
公开(公告)号：US07132362B2
公开(公告)日：2006-11-07
申请号：US10003386
申请日：2001-10-30
申请人： Mun-Mo Jeong
发明人： Mun-Mo Jeong
IPC分类号： H01L21/4763 , H01L21/302 , H01L21/469
CPC分类号： H01L21/76849 , H01L21/76802 , H01L21/76805 , H01L21/76865
摘要： A semiconductor device having a contact hole capable of maintaining contact resistance of a contact connecting multi-layered interconnections with each other and a method for manufacturing the same are provided. An interconnection layer, a capping layer, and an etching stopper are sequentially formed on a semiconductor substrate. An interlayer insulating layer is deposited over the resulting structure. The etching stopper is formed of a material having a high etching selectivity with respect to the interlayer insulating layer. Then a first contact hole is formed to expose the surface of the etching stopper by etching a predetermined portion of the interlayer insulating layer. Either the etching stopper exposed by the first contact hole or the etching stopper exposed by the first contact hole and part of the capping layer are etched to form a second contact hole. As a result, it is possible to manufacture a semiconductor device having uniform contact resistance over the surface of the semiconductor substrate, irrespective of topology of a lower interconnection layer or the degree of flatness of the interlayer insulating layer covering the lower interconnection layer.

9. 发明授权

US5780334A Method of fabricating capacitor of semiconductor memory device 失效
标题翻译：制造半导体存储器件电容器的方法
公开(公告)号：US5780334A
公开(公告)日：1998-07-14
申请号：US730705
申请日：1996-10-11
申请人： Jun-Hee Lim , Mun-Mo Jeong
发明人： Jun-Hee Lim , Mun-Mo Jeong
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method of fabricating a capacitor of a semiconductor memory device includes the steps of: forming an interlevel insulating layer on a semiconductor substrate on which the capacitor will be formed, selectively etching a portion of the interlevel insulating layer placed on a capacitor forming portion to form a capacitor node hole, and forming a first temporary layer on the interlevel insulating layer, including a portion of the interlevel insulating layer in which the capacitor node hole is formed; forming a contact hole beneath the capacitor node hole in a capacitor contact portion; forming a conductive layer on the first temporary layer to bury the contact hole and the capacitor node hole, and then forming a second temporary layer on the conductive layer; etching back the second temporary layer through anisotropic etching process to expose the conductive layer, and to simultaneously form a temporary pillar layer inside the capacitor node hole, the temporary pillar layer being substantially surrounded by the conductive layer; removing a portion of the conductive layer placed on a portion other than the capacitor forming portion, to form a first capacitor electrode and to expose at least a portion of the first temporary layer; and removing remaining portions of the first and second temporary layers to expose an upper portion of the first capacitor electrode, forming a dielectric layer on a surface of the first capacitor electrode, and forming a second capacitor electrode on a surface of the dielectric layer.
摘要翻译：制造半导体存储器件的电容器的方法包括以下步骤：在要形成电容器的半导体衬底上形成层间绝缘层，选择性地蚀刻位于电容器形成部分上的层间绝缘层的一部分以形成电容器节点孔，并且在所述层间绝缘层上形成包括形成有所述电容器节点孔的所述层间绝缘层的一部分的第一临时层; 在电容器接触部分中的电容器节点孔下方形成接触孔; 在所述第一临时层上形成导电层以埋置所述接触孔和所述电容器节点孔，然后在所述导电层上形成第二临时层; 通过各向异性蚀刻工艺蚀刻第二临时层以暴露导电层，并且在电容器节点孔内同时形成临时柱层，临时柱层基本上被导电层包围; 去除放置在除电容器形成部分之外的部分上的导电层的一部分，以形成第一电容器电极并暴露第一临时层的至少一部分; 以及去除所述第一和第二临时层的剩余部分以暴露所述第一电容器电极的上部，在所述第一电容器电极的表面上形成介电层，以及在所述电介质层的表面上形成第二电容器电极。

10. 发明授权

US5795802A Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5795802A
公开(公告)日：1998-08-18
申请号：US922384
申请日：1997-09-03
申请人： Sang-Gi Ko , Mun-Mo Jeong
发明人： Sang-Gi Ko , Mun-Mo Jeong
IPC分类号： H01L21/336 , H01L21/316 , H01L21/76 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/823857
摘要： A method for manufacturing a semiconductor device, the method includes the steps of forming an n-type well and a p-type well under a surface of a semiconductor substrate, forming a pad oxide layer having a first thickness on the p-type well and a second thickness on the n-type well, the first thickness being greater than the second thickness, and forming a field oxide layer between the n-type well and the p-type well, the field oxide layer having less bird's beak on the n-type well than on the p-type well.
摘要翻译：一种制造半导体器件的方法，该方法包括以下步骤：在半导体衬底的表面下形成n型阱和p型阱，在p型阱上形成具有第一厚度的衬垫氧化物层，以及在n型阱上的第二厚度，第一厚度大于第二厚度，并且在n型阱和p型阱之间形成场氧化物层，在n型阱上具有较少鸟喙的场氧化物层类型比p型井好。

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