专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080043557A1 Semiconductor devices the include a fuse part including an antifuse and protection circuit 失效
标题翻译：半导体器件包括包括反熔丝和保护电路的熔丝部分
公开(公告)号：US20080043557A1
公开(公告)日：2008-02-21
申请号：US11800635
申请日：2007-05-07
申请人： Sang-Gi Ko
发明人： Sang-Gi Ko
IPC分类号： G11C17/18 , H01H37/76
CPC分类号： G11C17/18
摘要： A semiconductor device includes a fuse part including an antifuse that is connected between a first common node to which a high voltage that is higher than an internal boost voltage is applied and a first node. The fuse part is enabled in response to a program mode selection signal and an address signal so as to fuse the antifuse in response to the high voltage applied to the first common node and to set a voltage level of a second node. A latch circuit is configured to latch an output signal responsive to the voltage level of the second node when the fuse part is in a fused state. A protection circuit is configured to lower a voltage level at the first node when the fuse part is not enabled and the high voltage is applied to the first common node.
摘要翻译：半导体器件包括熔丝部分，其包括连接在施加高于内部升压电压的高电压的第一公共节点与第一节点之间的反熔丝。熔丝部分响应于编程模式选择信号和地址信号使能，以便响应于施加到第一公共节点的高电压来熔断反熔丝并设置第二节点的电压电平。闩锁电路被配置为当熔丝部分处于融合状态时，响应于第二节点的电压电平来锁存输出信号。保护电路被配置为当熔丝部分未使能并且高电压施加到第一公共节点时降低第一节点处的电压电平。

2. 发明授权

US06579757B2 Method for fabricating semiconductor device which prevents gates of a peripheral region from being oxidized 有权
标题翻译：制造防止外围区域的栅极氧化的半导体装置的方法
公开(公告)号：US06579757B2
公开(公告)日：2003-06-17
申请号：US09989489
申请日：2001-11-21
申请人： Jae Hyung Kim , Sang Gi Ko , Byoung Ock Song , Hee Joong Oh
发明人： Jae Hyung Kim , Sang Gi Ko , Byoung Ock Song , Hee Joong Oh
IPC分类号： H01L218242
CPC分类号： H01L27/112 , H01L21/823456 , H01L27/105 , H01L27/11286
摘要： A method of fabricating a semiconductor device, includes the steps of forming gates in a cell region and in a peripheral region of a substrate, forming a polysilicon layer over an entire surface of the resultant structure, partially removing portions of the polysilicon layer in the cell region to maintain the polysilicon layer of a predetermined thickness in the cell region, removing the predetermined thickness of the polysilicon layer both in the cell and peripheral regions, so that the resultant structure includes exposed gates in the cell region but no exposed gates in the peripheral region, and forming an insulating layer over the resultant structure.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在单元区域和衬底的周边区域中形成栅极，在所得结构的整个表面上形成多晶硅层，部分去除电池中多晶硅层的部分区域以保持单元区域中预定厚度的多晶硅层，在单元区域和外围区域中去除多晶硅层的预定厚度，使得所得结构包括在单元区域中的暴露的栅极，但在外围区域中没有暴露的栅极并在所得结构上形成绝缘层。

3. 发明授权

US5795802A Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5795802A
公开(公告)日：1998-08-18
申请号：US922384
申请日：1997-09-03
申请人： Sang-Gi Ko , Mun-Mo Jeong
发明人： Sang-Gi Ko , Mun-Mo Jeong
IPC分类号： H01L21/336 , H01L21/316 , H01L21/76 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/823857
摘要： A method for manufacturing a semiconductor device, the method includes the steps of forming an n-type well and a p-type well under a surface of a semiconductor substrate, forming a pad oxide layer having a first thickness on the p-type well and a second thickness on the n-type well, the first thickness being greater than the second thickness, and forming a field oxide layer between the n-type well and the p-type well, the field oxide layer having less bird's beak on the n-type well than on the p-type well.
摘要翻译：一种制造半导体器件的方法，该方法包括以下步骤：在半导体衬底的表面下形成n型阱和p型阱，在p型阱上形成具有第一厚度的衬垫氧化物层，以及在n型阱上的第二厚度，第一厚度大于第二厚度，并且在n型阱和p型阱之间形成场氧化物层，在n型阱上具有较少鸟喙的场氧化物层类型比p型井好。

4. 发明申请

US20140198560A1 MEMORY CELL AND MEMORY DEVICE HAVING THE SAME 有权
标题翻译：存储单元和具有该存储单元的存储器件
公开(公告)号：US20140198560A1
公开(公告)日：2014-07-17
申请号：US14083569
申请日：2013-11-19
申请人： Choong-Jae LEE , Kyoung-Mok SON , Sang-Gi KO , Si-Woo KIM
发明人： Choong-Jae LEE , Kyoung-Mok SON , Sang-Gi KO , Si-Woo KIM
IPC分类号： G11C11/4096
CPC分类号： G11C8/16 , G11C11/403 , H01L27/10805 , H01L27/1156
摘要： A memory cell includes a metal oxide semiconductor (MOS) capacitor including a gate coupled to a storage node and an electrode coupled to a synchronization control line. The MOS capacitor adds a coupling voltage to the gate based on a change in voltage on the synchronization control line. The coupling voltage may maintain the storage node within a predetermined range.
摘要翻译：存储单元包括金属氧化物半导体（MOS）电容器，其包括耦合到存储节点的栅极和耦合到同步控制线的电极。 MOS电容器基于同步控制线上的电压变化，向栅极增加耦合电压。耦合电压可以将存储节点维持在预定范围内。

5. 发明授权

US06340619B1 Capacitor and method of fabricating the same 失效
标题翻译：电容器及其制造方法
公开(公告)号：US06340619B1
公开(公告)日：2002-01-22
申请号：US08871780
申请日：1997-06-09
申请人： Sang-Gi Ko
发明人： Sang-Gi Ko
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/40
摘要： A capacitor includes a substrate, an insulating layer on the substrate, the insulating layer having a contact hole, a first storage node in the contact hole and on the insulating layer, a second storage node on a peripheral portion of the first storage node, the second storage node having a planar top surface, a dielectric layer on the surface of the first and second storage nodes, and a plate node on the dielectric layer.
摘要翻译：电容器包括基板，基板上的绝缘层，具有接触孔的绝缘层，接触孔中的第一存储节点和绝缘层上的第一存储节点，第一存储节点的外围部分上的第二存储节点，第二存储节点具有平坦的顶表面，在第一和第二存储节点的表面上的介电层以及介电层上的板节点。

6. 发明授权

US5731949A Structure of capacitor and method of frabricating same 失效
标题翻译：电容器的结构及其制造方法
公开(公告)号：US5731949A
公开(公告)日：1998-03-24
申请号：US742905
申请日：1996-11-01
申请人： Sang Gi Ko
发明人： Sang Gi Ko
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/08 , H01L27/108 , H01G4/06 , H01G7/00
CPC分类号： H01L27/10852 , H01L27/0805 , H01L27/10817 , Y10T29/435
摘要： A capacitor includes a substrate having a first trench, and a second trench, a first storage node having a first body and a first flange, the first body being on the first trench and having a first height and the first flange being extended at a top portion of the first body to a first length from the first body, a second storage node having a second body and a second flange, the second body being in the second trench and having a second height different from the first height of the first body, and the second flange being extended in a direction opposite to the first flange to a second length from the second length from the second body, a dielectric film on the surfaces of the first and second storage nodes, and a plate electrode on the dielectric film.
摘要翻译：电容器包括具有第一沟槽的衬底和第二沟槽，具有第一主体和第一凸缘的第一存储节点，第一主体位于第一沟槽上并具有第一高度，第一凸缘在顶部延伸所述第一主体的所述部分从所述第一主体到第一长度，第二存储节点具有第二主体和第二凸缘，所述第二主体位于所述第二沟槽中并具有与所述第一主体的所述第一高度不同的第二高度，并且所述第二凸缘沿着与所述第一凸缘相反的方向延伸到距所述第二主体的所述第二长度的第二长度，所述第一和第二存储节点的表面上的电介质膜和所述电介质膜上的平板电极。

7. 发明授权

US5950095A Semiconductor memory cell fabrication method 失效
标题翻译：半导体存储单元制造方法
公开(公告)号：US5950095A
公开(公告)日：1999-09-07
申请号：US847334
申请日：1997-04-23
申请人： Sang-Gi Ko
发明人： Sang-Gi Ko
IPC分类号： H01L21/762 , H01L21/8242 , H01L27/108 , H01L21/76
CPC分类号： H01L27/10844 , H01L21/762 , H01L27/10873
摘要： A semiconductor device includes a substrate having an active region between field oxide films, a gate formed on the substrate with a gate oxide therebetween, and a first impurity region formed adjacent to each side of the gate. A second impurity region is formed between the field oxide film and the first impurity region and a first insulating film with a contact hole exposes portions of the first and second impurity regions. An electrode formed in the contact hole such that the portions of the first and second impurity regions overlap an area in the substrate beneath the electrode. A method of forming an active region for a semiconductor device comprises the steps of: (a) forming a plurality of field oxide films in a prescribed pattern in x and y directions on a surface of a semiconductor substrate; (b) removing a bird beak portion of each of the plurality of field oxide films; and (c) doping a prescribed portion of an area of the semiconductor substrate, where each beak portion has been removed, with a prescribed concentration of a dopant.
摘要翻译：半导体器件包括在场氧化物膜之间具有有源区的衬底，在衬底上形成栅极氧化物的栅极和与栅极的每一侧相邻形成的第一杂质区。在场氧化膜和第一杂质区之间形成第二杂质区，具有接触孔的第一绝缘膜露出第一和第二杂质区的一部分。形成在所述接触孔中的电极，使得所述第一和第二杂质区的所述部分与所述电极下方的所述基板中的区域重叠。形成半导体器件的有源区的方法包括以下步骤：（a）在半导体衬底的表面上沿x和y方向以规定的图案形成多个场氧化膜; （b）去除多个场氧化膜中的每一个的鸟嘴部分; 和（c）以规定浓度的掺杂剂掺杂其中每个喙部分被去除的半导体衬底的面积的规定部分。

8. 发明授权

US07539074B2 Protection circuit with antifuse configured as semiconductor memory redundancy circuitry 失效
标题翻译：具有反熔丝的保护电路配置为半导体存储器冗余电路
公开(公告)号：US07539074B2
公开(公告)日：2009-05-26
申请号：US11800635
申请日：2007-05-07
申请人： Sang-Gi Ko
发明人： Sang-Gi Ko
IPC分类号： G11C17/16
CPC分类号： G11C17/18
摘要： A semiconductor device includes a fuse part including an antifuse that is connected between a first common node to which a high voltage that is higher than an internal boost voltage is applied and a first node. The fuse part is enabled in response to a program mode selection signal and an address signal so as to fuse the antifuse in response to the high voltage applied to the first common node and to set a voltage level of a second node. A latch circuit is configured to latch an output signal responsive to the voltage level of the second node when the fuse part is in a fused state. A protection circuit is configured to lower a voltage level at the first node when the fuse part is not enabled and the high voltage is applied to the first common node.
摘要翻译：半导体器件包括熔丝部分，其包括连接在施加高于内部升压电压的高电压的第一公共节点与第一节点之间的反熔丝。熔丝部分响应于编程模式选择信号和地址信号使能，以便响应于施加到第一公共节点的高电压来熔断反熔丝并设置第二节点的电压电平。闩锁电路被配置为当熔丝部分处于融合状态时，响应于第二节点的电压电平来锁存输出信号。保护电路被配置为当熔丝部分未使能并且高电压施加到第一公共节点时降低第一节点处的电压电平。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式