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1. 发明申请

US20100008137A1 NONVOLATILE MEMORY DEVICE AND PROGRAM OR ERASE METHOD USING THE SAME 失效
标题翻译：非易失性存储器件和使用其的程序或擦除方法
公开(公告)号：US20100008137A1
公开(公告)日：2010-01-14
申请号：US12493288
申请日：2009-06-29
申请人： Chae Kyu Jang , Seung Ho Chang , Young Soo Park , Jae Yun Kim , Se Chun Park
发明人： Chae Kyu Jang , Seung Ho Chang , Young Soo Park , Jae Yun Kim , Se Chun Park
IPC分类号： G11C16/06 , G11C16/04 , G11C7/06
CPC分类号： G11C16/10 , G11C16/14 , G11C16/28 , G11C16/30
摘要： A nonvolatile memory device includes a comparison unit configured to compare a reference voltage and a voltage of each of a plurality of nodes of a sample memory cell string, a state storage unit configured to store state information of each of memory cells depending on the corresponding comparison result of the comparison unit, and a high voltage generation unit configured to change a program start voltage depending on data stored in the state storage unit.
摘要翻译：非易失性存储器件包括：比较单元，被配置为比较采样存储单元串的多个节点的参考电压和电压;状态存储单元，被配置为根据相应的比较来存储每个存储器单元的状态信息比较单元的结果，以及被配置为根据存储在状态存储单元中的数据来改变程序开始电压的高电压生成单元。

2. 发明授权

US07872918B2 Nonvolatile memory device and program or erase method using the same 失效
标题翻译：非易失存储器件和使用其的程序或擦除方法
公开(公告)号：US07872918B2
公开(公告)日：2011-01-18
申请号：US12493288
申请日：2009-06-29
申请人： Chae Kyu Jang , Seung Ho Chang , Young Soo Park , Jae Yun Kim , Se Chun Park
发明人： Chae Kyu Jang , Seung Ho Chang , Young Soo Park , Jae Yun Kim , Se Chun Park
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C16/14 , G11C16/28 , G11C16/30
摘要： A nonvolatile memory device includes a comparison unit configured to compare a reference voltage and a voltage of each of a plurality of nodes of a sample memory cell string, a state storage unit configured to store state information of each of memory cells depending on the corresponding comparison result of the comparison unit, and a high voltage generation unit configured to change a program start voltage depending on data stored in the state storage unit.
摘要翻译：非易失性存储器件包括：比较单元，被配置为比较采样存储单元串的多个节点的参考电压和电压;状态存储单元，被配置为根据相应的比较来存储每个存储器单元的状态信息比较单元的结果，以及被配置为根据存储在状态存储单元中的数据来改变程序开始电压的高电压生成单元。

3. 发明授权

US08365026B2 Methods for performing fail test, block management, erasing and programming in a nonvolatile memory device 失效
标题翻译：用于在非易失性存储器件中执行故障测试，块管理，擦除和编程的方法
公开(公告)号：US08365026B2
公开(公告)日：2013-01-29
申请号：US12130994
申请日：2008-05-30
申请人： Jong Hyun Wang , Chae Kyu Jang , Se Chun Park
发明人： Jong Hyun Wang , Chae Kyu Jang , Se Chun Park
IPC分类号： G11C29/44 , G11C29/56
CPC分类号： G11C29/44 , G11C29/82 , G11C2029/1208 , G11C2029/4402
摘要： Methods for performing a fail test, block management, erase operations and program operations are used in a nonvolatile memory device having a block switch devoid of a fuse and a PMOS transistor. A method for performing a fail test in a nonvolatile memory device includes performing a fail test for a memory cell block; storing good block information in a block information store associated with the corresponding block when the memory cell block is a good block; and repeating the performing and storing steps for all memory cell blocks.
摘要翻译：在具有不具有熔丝和PMOS晶体管的块开关的非易失性存储器件中使用用于执行故障测试，块管理，擦除操作和编程操作的方法。用于在非易失性存储器件中执行故障测试的方法包括执行存储器单元块的故障测试; 当所述存储器单元块是良好块时，将良好块信息存储在与相应块相关联的块信息存储器中; 并重复执行和存储所有存储单元块的步骤。

4. 发明申请

US20090172482A1 METHODS FOR PERFORMING FAIL TEST, BLOCK MANAGEMENT, ERASING AND PROGRAMMING IN A NONVOLATILE MEMORY DEVICE 失效
标题翻译：在非易失性存储器件中执行失败测试，块管理，擦除和编程的方法
公开(公告)号：US20090172482A1
公开(公告)日：2009-07-02
申请号：US12130994
申请日：2008-05-30
申请人： Jong Hyun WANG , Chae Kyu Jang , Se Chun Park
发明人： Jong Hyun WANG , Chae Kyu Jang , Se Chun Park
IPC分类号： G11C29/08 , G06F11/26
CPC分类号： G11C29/44 , G11C29/82 , G11C2029/1208 , G11C2029/4402
摘要： Methods for performing a fail test, block management, erase operations and program operations are used in a nonvolatile memory device having a block switch devoid of a fuse and a PMOS transistor. A method for performing a fail test in a nonvolatile memory device includes performing a fail test for a memory cell block; storing good block information in a block information store associated with the corresponding block when the memory cell block is a good block; and repeating the performing and storing steps for all memory cell blocks.
摘要翻译：在具有不具有熔丝和PMOS晶体管的块开关的非易失性存储器件中使用用于执行故障测试，块管理，擦除操作和编程操作的方法。用于在非易失性存储器件中执行故障测试的方法包括执行存储器单元块的故障测试; 当所述存储器单元块是良好块时，将良好块信息存储在与相应块相关联的块信息存储器中; 并重复执行和存储所有存储单元块的步骤。

5. 发明授权

US08189388B2 Fuse circuit and flash memory device having the same 有权
标题翻译：保险丝电路和具有相同功能的闪存器件
公开(公告)号：US08189388B2
公开(公告)日：2012-05-29
申请号：US12839277
申请日：2010-07-19
申请人： Chae Kyu Jang
发明人： Chae Kyu Jang
IPC分类号： G11C11/34 , G11C16/06 , G11C17/00 , G11C17/18
CPC分类号： G11C17/16 , G11C17/18 , G11C29/785
摘要： A flash memory device includes a main cell array configured to have main memory cells for storing data and a redundancy cell array configured to have redundancy memory cells for repairing a failed memory cell of the main cell array. A page buffer circuit is configured to perform a program operation, a verifying operation and a read operation on the main cell array and the redundancy cell array. A repair circuit includes fuse circuits having fuse memory cells each of which is programmed in response to address information. The repair circuit is operated in response to a program state of the fuse memory cells and output a repair signal. A data input/output controller is configured to control input/output of data to/from the main memory cell or the redundancy memory cell in accordance with the repair signal outputted by the repair circuit.
摘要翻译：闪存器件包括：主单元阵列，被配置为具有用于存储数据的主存储单元;冗余单元阵列，被配置为具有用于修复主单元阵列的故障存储单元的冗余存储单元。页缓冲电路被配置为对主单元阵列和冗余单元阵列执行编程操作，验证操作和读操作。修复电路包括具有熔丝存储单元的熔丝电路，每个熔丝电路根据地址信息进行编程。修复电路响应于保险丝存储器单元的编程状态而被操作并输出修复信号。数据输入/输出控制器被配置为根据由修复电路输出的修复信号来控制到主存储器单元或冗余存储单元的数据输入/输出。

6. 发明申请

US20100284222A1 FUSE CIRCUIT AND FLASH MEMORY DEVICE HAVING THE SAME 有权
标题翻译：保险丝电路和具有该保险丝的闪存存储器件
公开(公告)号：US20100284222A1
公开(公告)日：2010-11-11
申请号：US12839277
申请日：2010-07-19
申请人： Chae Kyu Jang
发明人： Chae Kyu Jang
IPC分类号： G11C16/06 , G11C17/16
CPC分类号： G11C17/16 , G11C17/18 , G11C29/785
摘要： A flash memory device includes a main cell array configured to have main memory cells for storing data and a redundancy cell array configured to have redundancy memory cells for repairing a failed memory cell of the main cell array. A page buffer circuit is configured to perform a program operation, a verifying operation and a read operation on the main cell array and the redundancy cell array. A repair circuit includes fuse circuits having fuse memory cells each of which is programmed in response to address information. The repair circuit is operated in response to a program state of the fuse memory cells and output a repair signal. A data input/output controller is configured to control input/output of data to/from the main memory cell or the redundancy memory cell in accordance with the repair signal outputted by the repair circuit.
摘要翻译：闪存器件包括：主单元阵列，被配置为具有用于存储数据的主存储单元;冗余单元阵列，被配置为具有用于修复主单元阵列的故障存储单元的冗余存储单元。页缓冲电路被配置为对主单元阵列和冗余单元阵列执行编程操作，验证操作和读操作。修复电路包括具有熔丝存储单元的熔丝电路，每个熔丝电路根据地址信息进行编程。修复电路响应于保险丝存储器单元的编程状态而被操作并输出修复信号。数据输入/输出控制器被配置为根据由修复电路输出的修复信号来控制到主存储器单元或冗余存储单元的数据输入/输出。

7. 发明授权

US07499363B2 Semiconductor memory apparatus capable of reducing ground noise 有权
标题翻译：能够降低地面噪声的半导体存储装置
公开(公告)号：US07499363B2
公开(公告)日：2009-03-03
申请号：US11637080
申请日：2006-12-12
申请人： Dong Keun Kim , Chae Kyu Jang
发明人： Dong Keun Kim , Chae Kyu Jang
IPC分类号： G11C5/14 , G11C5/06 , G11C8/00
CPC分类号： G11C5/14 , G11C7/02
摘要： A semiconductor memory apparatus includes a bank that includes a core block where a memory cell array is disposed and a control block to drive the memory cell array, a ground power supply pad that is supplied with a ground power through a ground line, a switch that connects the ground line and the core block, and a block control unit that controls an on/off operation of the switch.
摘要翻译：一种半导体存储装置，具备包括配置有存储单元阵列的芯块和驱动存储单元阵列的控制块的存储体，通过地线提供接地电力的接地电源焊盘，连接地线和核心块，以及块控制单元，其控制开关的开/关操作。

8. 发明申请

US20090257302A1 Semiconductor memory apparatus capable of reducing ground noise 有权
标题翻译：能够降低地面噪声的半导体存储装置
公开(公告)号：US20090257302A1
公开(公告)日：2009-10-15
申请号：US12359623
申请日：2009-01-26
申请人： Chae Kyu Jang , Dong Keun Kim
发明人： Chae Kyu Jang , Dong Keun Kim
IPC分类号： G11C5/14 , G11C8/00 , G11C7/00
CPC分类号： G11C5/14 , G11C7/02
摘要： An apparatus includes a plurality of first driving signal driving units, and generates a first driving signal by driving an input signal, a plurality of second driving signal driving units, each of which drives an input signal and generates a second driving signal, a timing control unit that controls each of the first driving signal driving units such that a predetermined time difference is generated between an enable timing of the first driving signal and an enable timing of the second driving signal, a plurality of sense amplifier driving units, each of which generates a first driving level and a second driving level according to the first driving signal and the second driving signal, and a plurality of sense amplifiers that are provided for respective bit line pairs, and each include first type switching elements operating according to the first driving level and second type switching elements operating according to the second driving level.
摘要翻译：一种装置包括多个第一驱动信号驱动单元，并通过驱动输入信号产生第一驱动信号;多个第二驱动信号驱动单元，其驱动输入信号并产生第二驱动信号;定时控制控制每个第一驱动信号驱动单元的单元，使得在第一驱动信号的使能定时和第二驱动信号的使能定时之间产生预定时间差;多个读出放大器驱动单元，其产生根据第一驱动信号和第二驱动信号的第一驱动电平和第二驱动电平以及针对各个位线对设置的多个读出放大器，并且各自包括根据第一驱动电平工作的第一类型的开关元件以及根据第二驱动电平工作的第二类型的开关元件。

9. 发明申请

US20090122615A1 NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20090122615A1
公开(公告)日：2009-05-14
申请号：US12049253
申请日：2008-03-14
申请人： Chae Kyu Jang , Joong Seob Yang , Duck Ju Kim , Jong Hyun Wang , Seong Hun Park
发明人： Chae Kyu Jang , Joong Seob Yang , Duck Ju Kim , Jong Hyun Wang , Seong Hun Park
IPC分类号： G11C16/06
CPC分类号： G11C16/349
摘要： Program voltages of a non-volatile memory device are controlled variably according to a program/erase operation count. The non-volatile memory device includes a program voltage supply unit for applying a program voltage to a memory cell, a program/erase count storage unit for storing a total program/erase operation count of the non-volatile memory device, a program start voltage storage unit for storing levels of program start voltages to be differently supplied according to the program/erase operation count, and a program voltage controller for controlling the program start voltage according to the program/erase operation count.
摘要翻译：根据编程/擦除操作计数可变地控制非易失性存储器件的编程电压。非易失性存储器件包括用于将程序电压施加到存储单元的编程电压供应单元，用于存储非易失性存储器件的总编程/擦除操作计数的程序/擦除计数存储单元，程序启动电压存储单元，用于存储根据编程/擦除操作计数而不同地提供的程序启动电压的电平;以及编程电压控制器，用于根据编程/擦除操作计数来控制程序启动电压。

10. 发明授权

US07835214B2 Semiconductor memory apparatus capable of reducing ground noise 有权
公开(公告)号：US07835214B2
公开(公告)日：2010-11-16
申请号：US12359606
申请日：2009-01-26
申请人： Dong Keum Kim , Chae Kyu Jang
发明人： Dong Keum Kim , Chae Kyu Jang
IPC分类号： G11C5/14 , G11C5/02 , G11C5/06 , G11C8/00
CPC分类号： G11C5/14 , G11C7/02
摘要： An apparatus includes a plurality of first driving signal driving units, and generates a first driving signal by driving an input signal, a plurality of second driving signal driving units, each of which drives an input signal and generates a second driving signal, a timing control unit that controls each of the first driving signal driving units such that a predetermined time difference is generated between an enable timing of the first driving signal and an enable timing of the second driving signal, a plurality of sense amplifier driving units, each of which generates a first driving level and a second driving level according to the first driving signal and the second driving signal, and a plurality of sense amplifiers that are provided for respective bit line pairs, and each include first type switching elements operating according to the first driving level and second type switching elements operating according to the second driving level.

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