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1. 发明申请

US20100002495A1 Column Selectable Self-Biasing Virtual Voltages for SRAM Write Assist 有权
标题翻译：用于SRAM写入辅助的列选择自偏置虚拟电压
公开(公告)号：US20100002495A1
公开(公告)日：2010-01-07
申请号：US12167300
申请日：2008-07-03
申请人： Chad Allen Adams , George M. Braceras , Todd A. Christensen , Harold Pilo
发明人： Chad Allen Adams , George M. Braceras , Todd A. Christensen , Harold Pilo
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C11/417 , G11C11/41 , G11C11/419
摘要： A static random access memory decoder circuit includes a first cell supply line coupled to provide a first column of memory cells a first cell supply voltage and a second cell supply line coupled to provide a first column of memory cells a first cell supply voltage. The decoder circuit further includes a write assist circuit having a first threshold transistor coupled to the first cell supply line and a second threshold transistor coupled to the second cell supply line. In response to a write assist signal, the write assist circuit connects one of the first and second cell supply lines selected by control circuitry to an associated one of the first and second threshold transistors, such that a cell supply voltage of the selected one of the first and second cell supply lines is reduced toward the threshold voltage of the threshold transistor.
摘要翻译：静态随机存取存储器解码器电路包括第一单元电源线，其被耦合以提供第一列存储器单元第一单元电源电压和耦合以提供第一列存储器单元的第一单元电源电压的第二单元电源线。解码器电路还包括具有耦合到第一单元电源线的第一阈值晶体管和耦合到第二单元电源线的第二阈值晶体管的写辅助电路。响应于写入辅助信号，写入辅助电路将由控制电路选择的第一和第二单元电源线之一连接到第一和第二阈值晶体管中的相关联的一个，使得所选择的一个的单元电源电压第一和第二电池供应线路朝阈值晶体管的阈值电压减小。

2. 发明授权

US07817481B2 Column selectable self-biasing virtual voltages for SRAM write assist 有权
标题翻译：列可选择自偏压虚拟电压用于SRAM写入辅助
公开(公告)号：US07817481B2
公开(公告)日：2010-10-19
申请号：US12167300
申请日：2008-07-03
申请人： Chad Allen Adams , George M. Braceras , Todd A. Christensen , Harold Pilo
发明人： Chad Allen Adams , George M. Braceras , Todd A. Christensen , Harold Pilo
IPC分类号： G11C7/22 , G11C11/00 , G11C5/14
CPC分类号： G11C11/417 , G11C11/41 , G11C11/419
摘要： A static random access memory decoder circuit includes a first cell supply line coupled to provide a first column of memory cells a first cell supply voltage and a second cell supply line coupled to provide a first column of memory cells a first cell supply voltage. The decoder circuit further includes a write assist circuit having a first threshold transistor coupled to the first cell supply line and a second threshold transistor coupled to the second cell supply line. In response to a write assist signal, the write assist circuit connects one of the first and second cell supply lines selected by control circuitry to an associated one of the first and second threshold transistors, such that a cell supply voltage of the selected one of the first and second cell supply lines is reduced toward the threshold voltage of the threshold transistor.
摘要翻译：静态随机存取存储器解码器电路包括第一单元电源线，其被耦合以提供第一列存储器单元第一单元电源电压和耦合以提供第一列存储器单元的第一单元电源电压的第二单元电源线。解码器电路还包括具有耦合到第一单元电源线的第一阈值晶体管和耦合到第二单元电源线的第二阈值晶体管的写辅助电路。响应于写入辅助信号，写入辅助电路将由控制电路选择的第一和第二单元电源线之一连接到第一和第二阈值晶体管中的相关联的一个，使得所选择的一个的单元电源电压第一和第二电池供应线路朝阈值晶体管的阈值电压减小。

3. 发明申请

US20120075919A1 Methods and Systems for Adjusting Wordline Up-Level Voltage to Improve Production Yield Relative to SRAM-Cell Stability 有权
标题翻译：用于调整字面上升电压的方法和系统，以提高相对于SRAM单元稳定性的产量
公开(公告)号：US20120075919A1
公开(公告)日：2012-03-29
申请号：US12892191
申请日：2010-09-28
申请人： Igor Arsovski , George M. Braceras , Kevin W. Gorman , Robert M. Houle , Harold Pilo
发明人： Igor Arsovski , George M. Braceras , Kevin W. Gorman , Robert M. Houle , Harold Pilo
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C8/08
摘要： Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and pull-down devices and 2) the pull-up devices in the bitcells of the SRAM. These relative strengths are then used to adjust the wordline up-level voltage, if needed, to decrease the likelihood of the SRAM experiencing a stability failure. Corresponding systems are provided for determining the relative strengths of the devices of interest, for determining the amount of up-level voltage adjustment needed, and for selecting and setting the up-level voltage.
摘要翻译：在制造的SRAM中设置字线上电压的方法。在一个示例中，该方法包括确定1）通过栅极和下拉器件的组合的相对速度或强度，以及2）SRAM的位单元中的上拉器件。然后，如果需要，这些相对强度可用于调整字线上电压，以降低SRAM遇到稳定性故障的可能性。提供相应的系统用于确定感兴趣的装置的相对强度，用于确定所需的上限电压调整量以及用于选择和设定上限电压。

4. 发明授权

US07894291B2 Circuit and method for controlling a standby voltage level of a memory 有权
标题翻译：用于控制存储器的待机电压电平的电路和方法
公开(公告)号：US07894291B2
公开(公告)日：2011-02-22
申请号：US11162847
申请日：2005-09-26
申请人： George M. Braceras , John A. Fifield , Harold Pilo
发明人： George M. Braceras , John A. Fifield , Harold Pilo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147
摘要： A memory is provided which can be operated at an active rate of power consumption in an active operational mode and at a predetermined reduced rate of power consumption in a standby operational mode. The memory includes a current generating circuit which is operable to supply a predetermined magnitude of current to a sample power supply input terminal of a sample memory cell representative of memory cells of the memory, the predetermined magnitude of current corresponding to the predetermined reduced rate of power consumption. A voltage follower circuit is operable to output a standby voltage level equal to a voltage level at the sample power supply input terminal when the predetermined magnitude of current is supplied thereto. A memory cell array of the memory is operable to store data. In the standby operational mode, a switching circuit is operable to supply power at the standby voltage level to a power supply input terminal of the memory cell array. This permits data to remain stored in the memory during the standby mode. During an active operational mode, the switching circuit is operable to connect the power supply input terminal at the power supply to supply power at the active voltage level to the memory cell array. During the active operational mode, data can be stored into the memory cell array and retrieved from the memory cell array.
摘要翻译：提供一种存储器，其可以在主动操作模式中以在备用操作模式中以预定的降低的功率消耗速率以有效的功率消耗速率操作。存储器包括电流产生电路，其可操作以向代表存储器的存储器单元的采样存储单元的采样电源输入端提供预定大小的电流，与预定的降低的功率比相对应的预定电流值消费。电压跟随器电路可操作以当提供预定电流大小时输出等于采样电源输入端的电压电平的备用电压电平。存储器的存储单元阵列可操作以存储数据。在待机操作模式中，切换电路可操作以将备用电压电平的电力提供给存储单元阵列的电源输入端。这在待机模式期间允许数据保存在存储器中。在有效操作模式期间，开关电路可操作地连接电源处的电源输入端，以将有源电压电平的电力提供给存储单元阵列。在主动操作模式期间，可将数据存储到存储单元阵列中并从存储单元阵列检索。

5. 发明授权

US06967861B2 Method and apparatus for improving cycle time in a quad data rate SRAM device 有权
标题翻译：用于改善四倍数据速率SRAM器件中的周期时间的方法和装置
公开(公告)号：US06967861B2
公开(公告)日：2005-11-22
申请号：US10708379
申请日：2004-02-27
申请人： George M. Braceras , Harold Pilo
发明人： George M. Braceras , Harold Pilo
IPC分类号： G11C8/00 , G11C11/00 , G11C11/413
CPC分类号： G11C11/413
摘要： A method for implementing a self-timed, read to write operation in a memory storage device. In an exemplary embodiment, the method includes capturing a read address during a first half of a current clock cycle, and commencing a read operation so as to read data corresponding to the captured read address onto a pair of bit lines. A write operation is commenced for the current clock cycle so as to cause write data to appear on the pair of bit lines as soon as the read data from the captured read address is amplified by a sense amplifier, wherein the write operation uses a previous write address captured during a preceding clock cycle. A current write address is captured during a second half of the current clock cycle, said current write address used for a write operation implemented during a subsequent clock cycle, wherein the write operation for the current clock cycle is timed independent of the current write address captured during said second half of the current clock cycle.
摘要翻译：一种用于在存储器存储设备中实现自定时的读写操作的方法。在一个示例性实施例中，该方法包括在当前时钟周期的前半部分期间捕获读取地址，并开始读取操作，以便将对应于所捕获的读取地址的数据读取到一对位线上。一旦当前时钟周期开始写入操作，以便一旦来自捕获的读取地址的读取数据被读出放大器放大，就会使写入数据出现在该对位线上，其中写入操作使用先前的写入在前一个时钟周期捕获的地址。在当前时钟周期的后半段期间捕获当前写入地址，所述当前写入地址用于在随后的时钟周期期间实现的写入操作，其中当前时钟周期的写入操作被独立于捕获的当前写入地址在当前时钟周期的后半段。

6. 发明授权

US06922076B2 Scalable termination 失效
标题翻译：可扩展终止
公开(公告)号：US06922076B2
公开(公告)日：2005-07-26
申请号：US10604936
申请日：2003-08-27
申请人： George M. Braceras , Reid C. Hutchins , Harold Pilo
发明人： George M. Braceras , Reid C. Hutchins , Harold Pilo
IPC分类号： H04L25/02 , H03K17/16
CPC分类号： H04L25/0298 , H04L25/0278
摘要： In a first aspect, a first method is provided for providing multiple termination values using a plurality of binary termination signals. The first method includes the steps of (1) determining a characteristic impedance of a first port by generating a plurality of binary termination signals; and (2) modifying a characteristic impedance of a second port by manipulating one or more of the plurality of binary termination signals. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种使用多个二进制终止信号来提供多个终止值的第一方法。第一种方法包括以下步骤：（1）通过产生多个二进制终止信号来确定第一端口的特性阻抗; 和（2）通过操纵多个二进制终止信号中的一个或多个来修改第二端口的特性阻抗。提供了许多其他方面。

7. 发明授权

US06897674B2 Adaptive integrated circuit based on transistor current measurements 有权
标题翻译：基于晶体管电流测量的自适应集成电路
公开(公告)号：US06897674B2
公开(公告)日：2005-05-24
申请号：US10604186
申请日：2003-06-30
申请人： George M. Braceras , Harold Pilo
发明人： George M. Braceras , Harold Pilo
IPC分类号： G01R31/30 , G01R31/26
CPC分类号： G01R31/3004
摘要： A method of tuning an integrated circuit on an integrated circuit chip including: performing a drain current at saturation measurement of one or more test field effect transistors on the integrated circuit chip; selectively programming fuses of a bank of fuses on the integrated circuit chip based on the drain current at saturation measurement; and tuning an output of the integrated circuit based on a pattern of blown and un-blown fuses in the bank of fuses.
摘要翻译：一种对集成电路芯片上的集成电路进行调谐的方法，包括：在集成电路芯片上的一个或多个测试场效应晶体管的饱和测量时执行漏极电流; 基于饱和度测量时的漏极电流有选择地对集成电路芯片上的熔丝组进行熔丝; 并根据保险丝库中的熔断和未熔断保险丝的模式调整集成电路的输出。

8. 发明授权

US08582351B2 Methods and systems for adjusting wordline up-level voltage to improve production yield relative to SRAM-cell stability 有权
标题翻译：用于调整字线上电压的方法和系统，以提高相对于SRAM单元稳定性的产量
公开(公告)号：US08582351B2
公开(公告)日：2013-11-12
申请号：US12892191
申请日：2010-09-28
申请人： Igor Arsovski , George M. Braceras , Kevin W. Gorman , Robert M. Houle , Harold Pilo
发明人： Igor Arsovski , George M. Braceras , Kevin W. Gorman , Robert M. Houle , Harold Pilo
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C8/08
摘要： Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and pull-down devices and 2) the pull-up devices in the bitcells of the SRAM. These relative strengths are then used to adjust the wordline up-level voltage, if needed, to decrease the likelihood of the SRAM experiencing a stability failure. Corresponding systems are provided for determining the relative strengths of the devices of interest, for determining the amount of up-level voltage adjustment needed, and for selecting and setting the up-level voltage.
摘要翻译：在制造的SRAM中设置字线上电压的方法。在一个示例中，该方法包括确定1）通过栅极和下拉器件的组合的相对速度或强度，以及2）SRAM的位单元中的上拉器件。然后，如果需要，这些相对强度可用于调整字线上电压，以降低SRAM遇到稳定性故障的可能性。提供相应的系统用于确定感兴趣的装置的相对强度，用于确定所需的上限电压调整量以及用于选择和设定上限电压。

9. 发明授权

US07904658B2 Structure for power-efficient cache memory 有权
标题翻译：高效能高效缓存的结构
公开(公告)号：US07904658B2
公开(公告)日：2011-03-08
申请号：US11851128
申请日：2007-09-06
申请人： Wagdi W. Abadeer , George M. Braceras , John A. Fifield , Harold Pilo
发明人： Wagdi W. Abadeer , George M. Braceras , John A. Fifield , Harold Pilo
IPC分类号： G06F12/00 , G06F1/00 , G06F1/26 , G11C5/14
CPC分类号： G06F12/0864 , G06F2212/1028 , G06F2212/601 , Y02D10/13
摘要： A design structure for a cache memory system (200) having a cache memory (204) partitioned into a number of banks, or “ways” (204A, 204B). The memory system includes a power controller (244) that selectively powers up and down the ways depending upon which way contains the data being sought by each incoming address (232) coming into the memory system.
摘要翻译：具有高速缓冲存储器（204）的高速缓冲存储器系统（200）的设计结构，所述高速缓冲存储器系统（200）被划分成多个存储体，或“路径”（204A，204B）。存储器系统包括功率控制器（244），功率控制器（244）根据包含正在进入存储器系统的每个输入地址（232）寻找的数据的方式选择性地向上和向下加电。

10. 发明授权

US07643357B2 System and method for integrating dynamic leakage reduction with write-assisted SRAM architecture 有权
标题翻译：将动态泄漏减少与写辅助SRAM架构相结合的系统和方法
公开(公告)号：US07643357B2
公开(公告)日：2010-01-05
申请号：US12032798
申请日：2008-02-18
申请人： George M. Braceras , Steven H. Lamphier , Harold Pilo , Vinod Ramadurai
发明人： George M. Braceras , Steven H. Lamphier , Harold Pilo , Vinod Ramadurai
IPC分类号： G11C5/14 , G11C11/00
CPC分类号： G11C11/417
摘要： A system for integrating dynamic leakage reduction with a write-assisted SRAM architecture includes power line selection circuitry associated with each column of one or more SRAM sub arrays, controlled by a selection signal that selects the associated sub array for a read or write operation, and by a column write signal that selects one of the columns of the sub arrays. The power line selection circuitry locally converts a first voltage, corresponding to a cell supply voltage for a read operation, to a second lower voltage to be supplied to each cell selected for a write operation, as to facilitate a write function. The power line selection circuitry also locally converts the first voltage to a third voltage to be supplied to power lines in unselected sub arrays, the third voltage also being lower than the first voltage so as to facilitate dynamic leakage reduction.
摘要翻译：用于将动态泄漏减少与写辅助SRAM结构集成的系统包括与由一个或多个SRAM子阵列的每列相关联的电源线选择电路，由选择信号控制，选择信号选择相关联的子阵列进行读或写操作，以及通过选择子阵列的列之一的列写入信号。电源线选择电路将对应于用于读取操作的单元电源电压的第一电压本地转换为要提供给被选择用于写入操作的每个单元的第二较低电压，以便于写入功能。电源线选择电路还将第一电压局部地转换为第三电压以提供给未选择的子阵列中的电力线，第三电压也低于第一电压，以便于动态泄漏降低。

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