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1. 发明授权

US07575855B2 Method of forming pattern 有权
标题翻译：形成图案的方法
公开(公告)号：US07575855B2
公开(公告)日：2009-08-18
申请号：US11145535
申请日：2005-06-03
申请人： Cha-Won Koh , Sang-Gyun Woo , Gi-Sung Yeo , Myoung-Ho Jung
发明人： Cha-Won Koh , Sang-Gyun Woo , Gi-Sung Yeo , Myoung-Ho Jung
IPC分类号： G03F1/00
CPC分类号： G03F7/11 , G03F7/0752 , G03F7/40 , H01L21/0271 , H01L21/0337 , H01L21/31138 , H01L21/31144
摘要： Disclosed is a method of forming a pattern. A first organic polymer layer is formed on a substrate on which an underlying layer, and then a second organic polymer layer, which has an opening partially exposing the first organic polymer layer, is formed on the first organic polymer layer. Next, a silicon-containing polymer layer is formed on the second organic polymer layer to cover the opening. The silicon-containing polymer layer is oxidized and simultaneously the second organic polymer layer and the first organic polymer layer are ashed by oxygen plasma to form a pattern having an anisotropy-shape. The underlying layer is etched using the silicon-containing polymer layer and the first organic polymer layer as an etching mask to form a pattern.
摘要翻译：公开了形成图案的方法。在第一有机聚合物层上形成第一有机聚合物层，在其上具有下层，然后形成具有部分暴露第一有机聚合物层的开口的第二有机聚合物层。接下来，在第二有机聚合物层上形成含硅聚合物层以覆盖开口。含硅聚合物层被氧化，同时第二有机聚合物层和第一有机聚合物层被氧等离子体灰化，形成具有各向异性形状的图案。使用含硅聚合物层和第一有机聚合物层作为蚀刻掩模蚀刻下层，以形成图案。

2. 发明授权

US07842451B2 Method of forming pattern 有权
标题翻译：形成图案的方法
公开(公告)号：US07842451B2
公开(公告)日：2010-11-30
申请号：US12511538
申请日：2009-07-29
申请人： Cha-Won Koh , Sang-Gyun Woo , Gi-Sung Yeo , Myoung-Ho Jung
发明人： Cha-Won Koh , Sang-Gyun Woo , Gi-Sung Yeo , Myoung-Ho Jung
IPC分类号： G03F1/00 , G03F7/00
CPC分类号： G03F7/11 , G03F7/0752 , G03F7/40 , H01L21/0271 , H01L21/0337 , H01L21/31138 , H01L21/31144
摘要： Disclosed is a method of forming a pattern. A first organic polymer layer is formed on a substrate on which an underlying layer, and then a second organic polymer layer, which has an opening partially exposing the first organic polymer layer, is formed on the first organic polymer layer. Next, a silicon-containing polymer layer is formed on the second organic polymer layer to cover the opening. The silicon-containing polymer layer is oxidized and simultaneously the second organic polymer layer and the first organic polymer layer are ashed by oxygen plasma to form a pattern having an anisotropy-shape. The underlying layer is etched using the silicon-containing polymer layer and the first organic polymer layer as an etching mask to form a pattern.
摘要翻译：公开了形成图案的方法。在第一有机聚合物层上形成第一有机聚合物层，在其上具有下层，然后形成具有部分暴露第一有机聚合物层的开口的第二有机聚合物层。接下来，在第二有机聚合物层上形成含硅聚合物层以覆盖开口。含硅聚合物层被氧化，同时第二有机聚合物层和第一有机聚合物层被氧等离子体灰化，形成具有各向异性形状的图案。使用含硅聚合物层和第一有机聚合物层作为蚀刻掩模蚀刻下层，以形成图案。

3. 发明申请

US20050282092A1 Method of forming pattern 有权
标题翻译：形成图案的方法
公开(公告)号：US20050282092A1
公开(公告)日：2005-12-22
申请号：US11145535
申请日：2005-06-03
申请人： Cha-Won Koh , Sang-Gyun Woo , Gi-Sung Yeo , Myoung-Ho Jung
发明人： Cha-Won Koh , Sang-Gyun Woo , Gi-Sung Yeo , Myoung-Ho Jung
IPC分类号： G03F7/00 , G03F7/075 , G03F7/11 , G03F7/40 , H01L21/027 , H01L21/033 , H01L21/311
CPC分类号： G03F7/11 , G03F7/0752 , G03F7/40 , H01L21/0271 , H01L21/0337 , H01L21/31138 , H01L21/31144
摘要： Disclosed is a method of forming a pattern. A first organic polymer layer is formed on a substrate on which an underlying layer, and then a second organic polymer layer, which has an opening partially exposing the first organic polymer layer, is formed on the first organic polymer layer. Next, a silicon-containing polymer layer is formed on the second organic polymer layer to cover the opening. The silicon-containing polymer layer is oxidized and simultaneously the second organic polymer layer and the first organic polymer layer are ashed by oxygen plasma to form a pattern having an anisotropy-shape. The underlying layer is etched using the silicon-containing polymer layer and the first organic polymer layer as an etching mask to form a pattern.
摘要翻译：公开了形成图案的方法。在第一有机聚合物层上形成第一有机聚合物层，在其上具有下层，然后形成具有部分暴露第一有机聚合物层的开口的第二有机聚合物层。接下来，在第二有机聚合物层上形成含硅聚合物层以覆盖开口。含硅聚合物层被氧化，同时第二有机聚合物层和第一有机聚合物层被氧等离子体灰化，形成具有各向异性形状的图案。使用含硅聚合物层和第一有机聚合物层作为蚀刻掩模蚀刻下层，以形成图案。

4. 发明申请

US20090291561A1 METHOD OF FORMING PATTERN 有权
标题翻译：形成图案的方法
公开(公告)号：US20090291561A1
公开(公告)日：2009-11-26
申请号：US12511538
申请日：2009-07-29
申请人： Cha-Won Koh , Sang-Gyun Woo , Gi-Sung Yeo , Myoung-Ho Jung
发明人： Cha-Won Koh , Sang-Gyun Woo , Gi-Sung Yeo , Myoung-Ho Jung
IPC分类号： H01L21/3065 , H01L21/306
CPC分类号： G03F7/11 , G03F7/0752 , G03F7/40 , H01L21/0271 , H01L21/0337 , H01L21/31138 , H01L21/31144
摘要： Disclosed is a method of forming a pattern. A first organic polymer layer is formed on a substrate on which an underlying layer, and then a second organic polymer layer, which has an opening partially exposing the first organic polymer layer, is formed on the first organic polymer layer. Next, a silicon-containing polymer layer is formed on the second organic polymer layer to cover the opening. The silicon-containing polymer layer is oxidized and simultaneously the second organic polymer layer and the first organic polymer layer are ashed by oxygen plasma to form a pattern having an anisotropy-shape. The underlying layer is etched using the silicon-containing polymer layer and the first organic polymer layer as an etching mask to form a pattern.
摘要翻译：公开了形成图案的方法。在第一有机聚合物层上形成第一有机聚合物层，在其上具有下层，然后形成具有部分暴露第一有机聚合物层的开口的第二有机聚合物层。接下来，在第二有机聚合物层上形成含硅聚合物层以覆盖开口。含硅聚合物层被氧化，同时第二有机聚合物层和第一有机聚合物层被氧等离子体灰化，形成具有各向异性形状的图案。使用含硅聚合物层和第一有机聚合物层作为蚀刻掩模蚀刻下层，以形成图案。

5. 发明申请

US20060131576A1 Semiconductor device having overlay measurement mark and method of fabricating the same 有权
公开(公告)号：US20060131576A1
公开(公告)日：2006-06-22
申请号：US11296921
申请日：2005-12-08
申请人： Cha-Won Koh , Sang-Gyun Woo , Seok-Hwan Oh , Gi-Sung Yeo , Hyun-Jae Kang , Jang-Ho Shin
发明人： Cha-Won Koh , Sang-Gyun Woo , Seok-Hwan Oh , Gi-Sung Yeo , Hyun-Jae Kang , Jang-Ho Shin
IPC分类号： H01L23/58
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7076 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： There are provided a semiconductor device having an overlay measurement mark, and a method of fabricating the same. The semiconductor device includes a scribe line region disposed on a semiconductor substrate. A first main scale layer having a first group of line and space patterns and a second group of line and space patterns is disposed on the scribe line region. Line-shaped second main scale patterns are disposed on space regions of the first group of the line and space patterns. Line-shaped vernier scale patterns are disposed on space regions of the second group of the line and space patterns. In the method, a first main scale layer having a first group of line and space patterns and a second group of line and space patterns is formed on a semiconductor substrate. Line-shaped second main scale patterns are formed on space regions of the first group of the line and space patterns. Line-shaped vernier scale patterns are formed on space regions of the second group of the line and space patterns.

6. 发明申请

US20070077524A1 Method for forming patterns of semiconductor device 失效
标题翻译：半导体器件形成方法
公开(公告)号：US20070077524A1
公开(公告)日：2007-04-05
申请号：US11529310
申请日：2006-09-29
申请人： Cha-Won Koh , Yool Kang , Sang-Gyun Woo , Seok-Hwan Oh , Gi-Sung Yeo , Ji-Young Lee
发明人： Cha-Won Koh , Yool Kang , Sang-Gyun Woo , Seok-Hwan Oh , Gi-Sung Yeo , Ji-Young Lee
IPC分类号： G03F7/26
CPC分类号： G03F7/40 , H01L21/0273 , H01L21/0337 , H01L21/0338
摘要： Provided is a method for forming patterns of a semiconductor device. According to the method, first mask patterns may be formed on a substrate, and second mask patterns may be formed on sidewalls of each first mask pattern. Third mask patterns may fill spaces formed between adjacent second mask patterns, and the second mask patterns may be removed. A portion of the substrate may then be removed using the first and third mask patterns as etch masks.
摘要翻译：提供了一种用于形成半导体器件的图案的方法。根据该方法，可以在衬底上形成第一掩模图案，并且可以在每个第一掩模图案的侧壁上形成第二掩模图案。第三掩模图案可以填充在相邻的第二掩模图案之间形成的空间，并且可以去除第二掩模图案。然后可以使用第一和第三掩模图案作为蚀刻掩模去除衬底的一部分。

7. 发明授权

US07862988B2 Method for forming patterns of semiconductor device 失效
标题翻译：半导体器件形成方法
公开(公告)号：US07862988B2
公开(公告)日：2011-01-04
申请号：US11529310
申请日：2006-09-29
申请人： Cha-Won Koh , Yool Kang , Sang-Gyun Woo , Seok-Hwan Oh , Gi-Sung Yeo , Ji-Young Lee
发明人： Cha-Won Koh , Yool Kang , Sang-Gyun Woo , Seok-Hwan Oh , Gi-Sung Yeo , Ji-Young Lee
IPC分类号： G03F7/26
CPC分类号： G03F7/40 , H01L21/0273 , H01L21/0337 , H01L21/0338
摘要： Provided is a method for forming patterns of a semiconductor device. According to the method, first mask patterns may be formed on a substrate, and second mask patterns may be formed on sidewalls of each first mask pattern. Third mask patterns may fill spaces formed between adjacent second mask patterns, and the second mask patterns may be removed. A portion of the substrate may then be removed using the first and third mask patterns as etch masks.
摘要翻译：提供了一种用于形成半导体器件的图案的方法。根据该方法，可以在衬底上形成第一掩模图案，并且可以在每个第一掩模图案的侧壁上形成第二掩模图案。第三掩模图案可以填充在相邻的第二掩模图案之间形成的空间，并且可以去除第二掩模图案。然后可以使用第一和第三掩模图案作为蚀刻掩模去除衬底的一部分。

8. 发明申请

US20070020565A1 Methods of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20070020565A1
公开(公告)日：2007-01-25
申请号：US11429071
申请日：2006-05-08
申请人： Cha-Won Koh , Sang-Gyun Woo , Jeong-Lim Nam , Kyeong-Koo Chi , Seok-Hwan Oh , Gi-Sung Yeo , Seung-Pil Chung , Heung-Sik Park
发明人： Cha-Won Koh , Sang-Gyun Woo , Jeong-Lim Nam , Kyeong-Koo Chi , Seok-Hwan Oh , Gi-Sung Yeo , Seung-Pil Chung , Heung-Sik Park
IPC分类号： G03F7/26
CPC分类号： G03F7/0035 , G03F7/40 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： Methods of fabricating a semiconductor device are provided. Methods of forming a finer pattern of a semiconductor device using a buffer layer for retarding, or preventing, bridge formation between patterns in the formation of a finer pattern below resolution limits of a photolithography process by double patterning are also provided. A first hard mask layer and/or a second hard mask layer may be formed on a layer of a substrate to be etched. A first etch mask pattern of a first pitch may be formed on the second hard mask layer. After a buffer layer is formed on the overall surface of the substrate, a second etch mask pattern of a second pitch may be formed thereon in a region between the first etch mask pattern. The buffer layer may be anisotropically etched using the second etch mask pattern as an etch mask, forming a buffer layer pattern. The second hard mask layer may be anisotropically etched using the first etch mask pattern and/or the buffer layer pattern as etch masks, forming a second hard mask pattern. The first hard mask layer may be anisotropically etched using the second hard mask pattern as an etch mask, forming a first hard mask pattern. The etched layer may be anisotropically etched using the first hard mask pattern as an etch mask.
摘要翻译：提供制造半导体器件的方法。还提供了使用缓冲层来形成更精细图案的半导体器件的方法，该缓冲层用于通过双重图案化来形成更精细图案的低于分辨率极限的光刻工艺的图案之间桥接形成。可以在要蚀刻的基板的层上形成第一硬掩模层和/或第二硬掩模层。可以在第二硬掩模层上形成第一间距的第一蚀刻掩模图案。在衬底的整个表面上形成缓冲层之后，可以在第一蚀刻掩模图案之间的区域中形成第二间距的第二蚀刻掩模图案。可以使用第二蚀刻掩模图案作为蚀刻掩模来各向异性地蚀刻缓冲层，形成缓冲层图案。可以使用第一蚀刻掩模图案和/或缓冲层图案作为蚀刻掩模对第二硬掩模层进行各向异性蚀刻，形成第二硬掩模图案。可以使用第二硬掩模图案作为蚀刻掩模对第一硬掩模层进行各向异性蚀刻，形成第一硬掩模图案。蚀刻层可以使用第一硬掩模图案作为蚀刻掩模进行各向异性蚀刻。

9. 发明授权

US07582899B2 Semiconductor device having overlay measurement mark and method of fabricating the same 有权
标题翻译：具有覆盖测量标记的半导体器件及其制造方法
公开(公告)号：US07582899B2
公开(公告)日：2009-09-01
申请号：US11296921
申请日：2005-12-08
申请人： Cha-Won Koh , Sang-Gyun Woo , Seok-Hwan Oh , Gi-Sung Yeo , Hyun-Jae Kang , Jang-Ho Shin
发明人： Cha-Won Koh , Sang-Gyun Woo , Seok-Hwan Oh , Gi-Sung Yeo , Hyun-Jae Kang , Jang-Ho Shin
IPC分类号： H01L23/58 , H01L29/10
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7076 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： There are provided a semiconductor device having an overlay measurement mark, and a method of fabricating the same. The semiconductor device includes a scribe line region disposed on a semiconductor substrate. A first main scale layer having a first group of line and space patterns and a second group of line and space patterns is disposed on the scribe line region. Line-shaped second main scale patterns are disposed on space regions of the first group of the line and space patterns. Line-shaped vernier scale patterns are disposed on space regions of the second group of the line and space patterns. In the method, a first main scale layer having a first group of line and space patterns and a second group of line and space patterns is formed on a semiconductor substrate. Line-shaped second main scale patterns are formed on space regions of the first group of the line and space patterns. Line-shaped vernier scale patterns are formed on space regions of the second group of the line and space patterns.
摘要翻译：提供了具有覆盖测量标记的半导体器件及其制造方法。半导体器件包括设置在半导体衬底上的划线区域。具有第一组线和空间图案的第一主刻度层和第二组线和空间图案组被布置在划线区域上。线形的第二主刻度图案设置在第一组线和空间图案的空间区域上。线状游标刻度图案设置在第二组线和空间图案的空间区域上。在该方法中，在半导体衬底上形成具有第一组线和空间图案组以及第二组线和空间图案组的第一主刻度层。线形的第二主刻度图案形成在第一组线和空间图案的空间区域上。在第二组线和空间图案的空间区域上形成线形游标刻度图案。

10. 发明授权

US07540970B2 Methods of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07540970B2
公开(公告)日：2009-06-02
申请号：US11429071
申请日：2006-05-08
申请人： Cha-Won Koh , Sang-Gyun Woo , Jeong-Lim Nam , Kyeong-Koo Chi , Seok-Hwan Oh , Gi-Sung Yeo , Seung-Pil Chung , Heung-Sik Park
发明人： Cha-Won Koh , Sang-Gyun Woo , Jeong-Lim Nam , Kyeong-Koo Chi , Seok-Hwan Oh , Gi-Sung Yeo , Seung-Pil Chung , Heung-Sik Park
IPC分类号： C03C15/00
CPC分类号： G03F7/0035 , G03F7/40 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： Methods of fabricating a semiconductor device are provided. Methods of forming a finer pattern of a semiconductor device using a buffer layer for retarding, or preventing, bridge formation between patterns in the formation of a finer pattern below resolution limits of a photolithography process by double patterning are also provided. A first hard mask layer and/or a second hard mask layer may be formed on a layer of a substrate to be etched. A first etch mask pattern of a first pitch may be formed on the second hard mask layer. After a buffer layer is formed on the overall surface of the substrate, a second etch mask pattern of a second pitch may be formed thereon in a region between the first etch mask pattern. The buffer layer may be anisotropically etched using the second etch mask pattern as an etch mask, forming a buffer layer pattern. The second hard mask layer may be anisotropically etched using the first etch mask pattern and/or the buffer layer pattern as etch masks, forming a second hard mask pattern. The first hard mask layer may be anisotropically etched using the second hard mask pattern as an etch mask, forming a first hard mask pattern. The etched layer may be anisotropically etched using the first hard mask pattern as an etch mask.
摘要翻译：提供制造半导体器件的方法。还提供了使用缓冲层来形成更精细图案的半导体器件的方法，该缓冲层用于通过双重图案化来形成更精细图案的低于分辨率极限的光刻工艺的图案之间桥接形成。可以在要蚀刻的基板的层上形成第一硬掩模层和/或第二硬掩模层。可以在第二硬掩模层上形成第一间距的第一蚀刻掩模图案。在衬底的整个表面上形成缓冲层之后，可以在第一蚀刻掩模图案之间的区域中形成第二间距的第二蚀刻掩模图案。可以使用第二蚀刻掩模图案作为蚀刻掩模来各向异性地蚀刻缓冲层，形成缓冲层图案。可以使用第一蚀刻掩模图案和/或缓冲层图案作为蚀刻掩模对第二硬掩模层进行各向异性蚀刻，形成第二硬掩模图案。可以使用第二硬掩模图案作为蚀刻掩模对第一硬掩模层进行各向异性蚀刻，形成第一硬掩模图案。蚀刻层可以使用第一硬掩模图案作为蚀刻掩模进行各向异性蚀刻。

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