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1. 发明授权

US07205216B2 Modification of electrical properties for semiconductor wafers 失效
标题翻译：半导体晶圆的电性能的改进
公开(公告)号：US07205216B2
公开(公告)日：2007-04-17
申请号：US10710700
申请日：2004-07-29
申请人： Casey J. Grant , Heidi L. Greer , Steven M. Shank , Michael C. Triplett
发明人： Casey J. Grant , Heidi L. Greer , Steven M. Shank , Michael C. Triplett
IPC分类号： H01L21/20 , H01L21/31
CPC分类号： H01L21/324 , H01L22/20
摘要： A method and structure for fabricating semiconductor wafers. The method comprises providing a plurality of semiconductor wafers. The plurality of semiconductor wafers comprises a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer is located adjacent to the second semiconductor wafer. A relationship is provided between a plurality of values for an electrical characteristic and a plurality of materials. A material is chosen from the plurality of materials existing in the relationship. A substructure is formed comprising the material sandwiched between a topside of the first semiconductor wafer and a backside of a portion of the of the second semiconductor wafer. The plurality of semiconductor wafers are placed into a furnace comprising an elevated temperature for processing resulting in a value for the first semiconductor wafer of the electrical characteristic that corresponds to said material in said relationship.
摘要翻译：一种用于制造半导体晶片的方法和结构。该方法包括提供多个半导体晶片。多个半导体晶片包括第一半导体晶片和第二半导体晶片。第一半导体晶片位于第二半导体晶片附近。在电特性和多种材料的多个值之间提供关系。从存在于该关系中的多种材料中选择材料。形成了包括夹在第一半导体晶片的顶侧和第二半导体晶片的一部分的背面之间的材料的子结构。将多个半导体晶片放置在包括用于处理的升高的温度的炉中，从而产生与所述关系中的所述材料对应的电特性的第一半导体晶片的值。

2. 发明申请

US20070194385A1 GATE STACKS 有权
标题翻译：门盖
公开(公告)号：US20070194385A1
公开(公告)日：2007-08-23
申请号：US11463039
申请日：2006-08-08
申请人： Dale W. Martin , Steven M. Shank , Michael C. Triplett , Deborah A. Tucker
发明人： Dale W. Martin , Steven M. Shank , Michael C. Triplett , Deborah A. Tucker
IPC分类号： H01L29/94
CPC分类号： H01L21/28247 , H01L21/28035 , H01L29/4916 , Y10S257/90
摘要： A gate stack structure. The structure includes (a) a semiconductor region and (b) a gate stack on top of the semiconductor region. The gate stack includes (i) a gate dielectric region on top of the semiconductor region, (ii) a first gate polysilicon region on top of the gate dielectric region, and (iii) a second gate polysilicon region on top of the first gate polysilicon region and doped with a type of dopants. The structure further includes (c) a diffusion barrier region and a spacer oxide region on a side wall of the gate stack. The diffusion barrier region (i) is sandwiched between the gate stack and the spacer oxide region and (ii) is in direct physical contact with both the first and second gate polysilicon regions, and (iii) comprises a material having a property of preventing a diffusion of oxygen-containing materials through the diffusion barrier region.
摘要翻译：门堆栈结构。该结构包括（a）半导体区域和（b）在半导体区域的顶部上的栅极堆叠。栅极堆叠包括（i）在半导体区域的顶部上的栅极电介质区域，（ii）位于栅极电介质区域顶部的第一栅极多晶硅区域，以及（iii）位于第一栅极多晶硅顶部的第二栅极多晶硅区域并掺杂一种掺杂剂。该结构还包括（c）栅叠层的侧壁上的扩散阻挡区和间隔氧化物区。扩散阻挡区域（i）夹在栅极叠层和间隔氧化物区域之间，（ii）与第一和第二栅极多晶硅区域直接物理接触，并且（iii）包括具有防止含氧材料通过扩散阻挡区扩散。

3. 发明授权

US07294554B2 Method to eliminate arsenic contamination in trench capacitors 失效
标题翻译：消除沟槽电容器中砷污染的方法
公开(公告)号：US07294554B2
公开(公告)日：2007-11-13
申请号：US11276024
申请日：2006-02-10
申请人： Marshall J. Fleming, Jr. , Mousa H. Ishaq , Steven M. Shank , Michael C. Triplett
发明人： Marshall J. Fleming, Jr. , Mousa H. Ishaq , Steven M. Shank , Michael C. Triplett
IPC分类号： H01L21/20
CPC分类号： H01L27/1087 , H01L29/66181 , H01L29/945
摘要： A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.
摘要翻译：提供了一种沟槽电容器结构，其中砷污染被基本上减少和/或基本上从通过具有高纵横比的沟槽开口的侧壁扩散到半导体衬底中被消除。本发明还提供一种制造这种沟槽电容器结构的方法以及在驱动退火步骤期间检测砷污染的方法。通过生产线运行的产品中砷的检测采用砷增强氧化的作用。也就是说，监测用于将砷驱入半导体衬底的高温氧化退火的厚度。对于大量的砷扩散，氧化速率将增加，导致较厚的氧化物层。如果检测到这样的事件，则可以重新加工已经通过工艺步骤形成掩埋板直到驱动退火的产品，以减少砷污染。

4. 发明授权

US07521748B2 Method to eliminate arsenic contamination in trench capacitors 失效
标题翻译：消除沟槽电容器中砷污染的方法
公开(公告)号：US07521748B2
公开(公告)日：2009-04-21
申请号：US11875503
申请日：2007-10-19
申请人： Marshall J. Fleming, Jr. , Mousa H. Ishaq , Steven M. Shank , Michael C. Triplett
发明人： Marshall J. Fleming, Jr. , Mousa H. Ishaq , Steven M. Shank , Michael C. Triplett
IPC分类号： H01L27/108
CPC分类号： H01L27/1087 , H01L29/66181 , H01L29/945
摘要： A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.
摘要翻译：提供了一种沟槽电容器结构，其中砷污染被基本上减少和/或基本上从通过具有高纵横比的沟槽开口的侧壁扩散到半导体衬底中被消除。本发明还提供一种制造这种沟槽电容器结构的方法以及在驱动退火步骤期间检测砷污染的方法。通过生产线运行的产品中砷的检测采用砷增强氧化的作用。也就是说，监测用于将砷驱入半导体衬底的高温氧化退火的厚度。对于大量的砷扩散，氧化速率将增加，导致较厚的氧化物层。如果检测到这样的事件，则可以重新加工已经通过工艺步骤形成掩埋板直到驱动退火的产品，以减少砷的污染。

5. 发明授权

US07378712B2 Gate stacks 有权
标题翻译：门堆叠
公开(公告)号：US07378712B2
公开(公告)日：2008-05-27
申请号：US11463039
申请日：2006-08-08
申请人： Dale W. Martin , Steven M. Shank , Michael C. Triplett , Deborah A. Tucker
发明人： Dale W. Martin , Steven M. Shank , Michael C. Triplett , Deborah A. Tucker
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28247 , H01L21/28035 , H01L29/4916 , Y10S257/90
摘要： A gate stack structure. The structure includes (a) a semiconductor region and (b) a gate stack on top of the semiconductor region. The gate stack includes (i) a gate dielectric region on top of the semiconductor region, (ii) a first gate polysilicon region on top of the gate dielectric region, and (iii) a second gate polysilicon region on top of the first gate polysilicon region and doped with a type of dopants. The structure further includes (c) a diffusion barrier region and a spacer oxide region on a side wall of the gate stack. The diffusion barrier region (i) is sandwiched between the gate stack and the spacer oxide region and (ii) is in direct physical contact with both the first and second gate polysilicon regions, and (iii) comprises a material having a property of preventing a diffusion of oxygen-containing materials through the diffusion barrier region.
摘要翻译：门堆栈结构。该结构包括（a）半导体区域和（b）在半导体区域的顶部上的栅极堆叠。栅极堆叠包括（i）在半导体区域的顶部上的栅极电介质区域，（ii）位于栅极电介质区域顶部的第一栅极多晶硅区域，以及（iii）位于第一栅极多晶硅顶部的第二栅极多晶硅区域并掺杂一种掺杂剂。该结构还包括（c）栅叠层的侧壁上的扩散阻挡区和间隔氧化物区。扩散阻挡区域（i）夹在栅极叠层和间隔氧化物区域之间，（ii）与第一和第二栅极多晶硅区域直接物理接触，并且（iii）包括具有防止含氧材料通过扩散阻挡区扩散。

6. 发明授权

US07157341B2 Gate stacks 失效
标题翻译：门堆叠
公开(公告)号：US07157341B2
公开(公告)日：2007-01-02
申请号：US10711742
申请日：2004-10-01
申请人： Dale W. Martin , Steven M. Shank , Michael C. Triplett , Deborah A. Tucker
发明人： Dale W. Martin , Steven M. Shank , Michael C. Triplett , Deborah A. Tucker
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L21/28247 , H01L21/28035 , H01L29/4916 , Y10S257/90
摘要： A structure and fabrication method for a gate stack used to define source/drain regions in a semiconductor substrate. The method comprises (a) forming a gate dielectric layer on top of the substrate, (b) forming a gate polysilicon layer on top of the gate dielectric layer, (c) implanting n-type dopants in a top layer of the gate polysilicon layer, (d) etching away portions of the gate polysilicon layer and the gate dielectric layer so as to form a gate stack on the substrate, and (e) thermally oxidizing side walls of the gate stack with the presence of a nitrogen-carrying gas. As a result, a diffusion barrier layer is formed at the same depth in the polysilicon material of the gate stack regardless of the doping concentration. Therefore, the n-type doped region of the gate stack has the same width as that of the undoped region of the gate stack.
摘要翻译：用于限定半导体衬底中的源极/漏极区域的栅堆叠的结构和制造方法。该方法包括：（a）在衬底的顶部形成栅介质层，（b）在栅极介电层的顶部形成栅极多晶硅层，（c）在栅极多晶硅层的顶层中注入n型掺杂剂，（d）蚀刻掉栅极多晶硅层和栅极电介质层的部分，以在衬底上形成栅极堆叠，以及（e）在存在氮气的气体下热氧化栅极堆叠的侧壁。结果，无论掺杂浓度如何，在栅叠层的多晶硅材料中，在相同的深度处形成扩散阻挡层。因此，栅极堆叠的n型掺杂区域具有与栅极堆叠的未掺杂区域相同的宽度。

7. 发明授权

US07951666B2 Deep trench capacitor and method 有权
标题翻译：深沟槽电容器及方法
公开(公告)号：US07951666B2
公开(公告)日：2011-05-31
申请号：US11872970
申请日：2007-10-16
申请人： Herbert L. Ho , Steven M. Shank
发明人： Herbert L. Ho , Steven M. Shank
IPC分类号： H01L21/8242
CPC分类号： H01L29/945 , H01L29/66181
摘要： Disclosed herein are embodiments of a deep trench capacitor structure and a method of forming the structure that incorporates a buried capacitor plate contact that is simultaneously formed using an adjacent deep trench. This configuration eliminates the need for additional photolithographic processing, thereby, optimizing process windows. This configuration further eliminates the need to form the deep trench capacitor through an N-doped diffusion region connector and, thereby, allows for greater design flexibility when connecting the deep trench capacitor to another integrated circuit structure (e.g., a memory cell or decoupling capacitor array). Also, disclosed herein are embodiments of another integrated circuit structure and method, and more specifically, a memory cell (e.g., a static random access memory (SRAM) cell)) and method of forming the memory cell that incorporates one or more of these deep trench capacitors in order to minimize or eliminate soft errors.
摘要翻译：这里公开了深沟槽电容器结构的实施例以及形成结构的方法，该结构包括使用相邻的深沟槽同时形成的埋入电容器板接触。该配置消除了对附加光刻处理的需要，从而优化处理窗口。该配置还消除了通过N掺杂扩散区连接器形成深沟槽电容器的需要，从而当将深沟槽电容器连接到另一集成电路结构（例如，存储器单元或去耦电容器阵列）。此外，本文公开的是另一集成电路结构和方法，更具体地，存储器单元（例如，静态随机存取存储器（SRAM）单元））的实施例）以及形成包含这些深度中的一个或多个的存储器单元的方法沟槽电容器，以减少或消除软错误。

8. 发明授权

US07893479B2 Deep trench in a semiconductor structure 有权
标题翻译：半导体结构中的深沟槽
公开(公告)号：US07893479B2
公开(公告)日：2011-02-22
申请号：US12538193
申请日：2009-08-10
申请人： June Cline , Dinh Dang , Mark Lagerquist , Jeffrey C. Maling , Lisa Y. Ninomiya , Bruce W. Porth , Steven M. Shank , Jessica A. Trapasso
发明人： June Cline , Dinh Dang , Mark Lagerquist , Jeffrey C. Maling , Lisa Y. Ninomiya , Bruce W. Porth , Steven M. Shank , Jessica A. Trapasso
IPC分类号： H01L29/108
CPC分类号： H01L21/31116 , H01L21/3081 , H01L21/3086 , H01L29/66181 , Y10S438/952
摘要： A semiconductor structure. A hard mask layer is on a top substrate surface of a semiconductor substrate. The hard mask layer includes a hard mask layer opening through which a portion of the top substrate surface is exposed to a surrounding ambient. The hard mask layer includes a pad oxide layer on the top substrate surface, a nitride layer on the pad oxide layer, a BSG (borosilicate glass) layer on top of the nitride layer, and an ARC (anti-reflective coating) layer on top of the BSG layer. A BSG side wall surface of the BSG layer is exposed to the surrounding ambient through the hard mask layer opening.
摘要翻译：半导体结构。硬掩模层位于半导体衬底的顶部衬底表面上。硬掩模层包括硬掩模层开口，顶部衬底表面的一部分暴露于周围的环境中。硬掩模层包括在顶部衬底表面上的衬垫氧化物层，衬垫氧化物层上的氮化物层，在氮化物层的顶部上的BSG（硼硅酸盐玻璃）层，以及顶部上的ARC（抗反射涂层）的BSG层。 BSG层的BSG侧壁表面通过硬掩模层开口暴露于周围环境。

9. 发明授权

US07694262B2 Deep trench capacitor and method of making same 失效
标题翻译：深沟槽电容器及其制作方法
公开(公告)号：US07694262B2
公开(公告)日：2010-04-06
申请号：US11872787
申请日：2007-10-16
申请人： Timothy Wayne Kemerer , Robert Mark Rassel , Steven M. Shank , Francis Roger White
发明人： Timothy Wayne Kemerer , Robert Mark Rassel , Steven M. Shank , Francis Roger White
IPC分类号： G06F17/50
CPC分类号： H01L29/945 , H01L29/66181
摘要： A trench capacitor, method of forming a trench capacitor and a design structure for a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers.
摘要翻译：沟槽电容器，形成沟槽电容器的方法以及沟槽电容器的设计结构。所述沟槽电容器包括：单晶硅衬底中的沟槽，在所述沟槽的侧壁和底部上的保形电介质衬垫; 填充未被衬垫填充的沟槽区域的导电多晶硅内板; 衬底中的导电掺杂外板，其围绕所述沟槽的侧壁和底部; 衬底中的掺杂硅区域; 在所述衬底的顶表面上暴露的所述掺杂硅区域的表面区域上的第一导电金属硅化物层; 在所述内板的在所述基板的顶表面处暴露的表面区域上的第二导电金属硅化物层; 以及在所述第一和第二金属硅化物层之间的所述衬底的顶表面上的绝缘环。

10. 发明申请

US20080315274A1 DEEP TRENCH CAPACITOR AND METHOD OF MAKING SAME 有权
标题翻译：深度电容电容器及其制造方法
公开(公告)号：US20080315274A1
公开(公告)日：2008-12-25
申请号：US11767616
申请日：2007-06-25
申请人： Timothy Wayne Kemerer , Robert Mark Rassel , Steven M. Shank , Francis Roger White
发明人： Timothy Wayne Kemerer , Robert Mark Rassel , Steven M. Shank , Francis Roger White
IPC分类号： H01L29/92 , H01L21/20
CPC分类号： H01L29/945 , H01L28/40
摘要： A trench capacitor and method of forming a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers.
摘要翻译：沟槽电容器和形成沟槽电容器的方法。所述沟槽电容器包括：单晶硅衬底中的沟槽，在所述沟槽的侧壁和底部上的保形电介质衬垫; 填充未被衬垫填充的沟槽区域的导电多晶硅内板; 衬底中的导电掺杂外板，其围绕所述沟槽的侧壁和底部; 衬底中的掺杂硅区域; 在所述衬底的顶表面上暴露的所述掺杂硅区域的表面区域上的第一导电金属硅化物层; 在所述内板的在所述基板的顶表面处暴露的表面区域上的第二导电金属硅化物层; 以及在所述第一和第二金属硅化物层之间的所述衬底的顶表面上的绝缘环。

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