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1. 发明授权

US5983257A System for signal processing using multiply-add operations 失效
标题翻译：使用多重加法运算的信号处理系统
公开(公告)号：US5983257A
公开(公告)日：1999-11-09
申请号：US578829
申请日：1995-12-26
申请人： Carole Dulong , Larry M. Mennemeier , Tuan H. Bui , Eiichi Kowashi , Alexander D. Peleg , Benny Eitan , Stephen A. Fischer , Benny Maytal , Millind Mittal
发明人： Carole Dulong , Larry M. Mennemeier , Tuan H. Bui , Eiichi Kowashi , Alexander D. Peleg , Benny Eitan , Stephen A. Fischer , Benny Maytal , Millind Mittal
IPC分类号： G06F7/544 , G06F9/302 , G06F7/00 , G06F7/52
CPC分类号： G06F9/30036 , G06F7/5443 , G06F9/30014 , G06F2207/3828
摘要： A computer system which includes a multimedia input device which generates an audio or video input signal and a processor coupled to the multimedia input device. The system further includes a storage device coupled to the processor and having stored therein a signal processing routine for multiplying and accumulating input values representative of the audio or video input signal. The signal processing routine, when executed by the processor, causes the processor to perform several steps. These steps include performing a packed multiply add on a first set of values packed into a first source and a second set of values packed into a second source each representing input signals to generate a packed intermediate result. The packed intermediate result is added to an accumulator to generate a packed accumulated result in the accumulator. These steps may be iterated with the first set of values and portions of the second set of values to the accumulator to generate the packed accumulated result. Subsequent thereto, the packed accumulated result in the accumulator is unpacked into a first result and a second result and the first result and the second result are added together to generate an accumulated result.
摘要翻译：一种计算机系统，其包括产生音频或视频输入信号的多媒体输入设备和耦合到所述多媒体输入设备的处理器。该系统还包括耦合到处理器并且在其中存储有用于乘以和累加表示音频或视频输入信号的输入值的信号处理例程的存储装置。信号处理程序在由处理器执行时使处理器执行几个步骤。这些步骤包括对打包到第一源的第一组值进行压缩乘法加法，并将第二组值打包到表示输入信号的第二源中，以生成打包的中间结果。将打包的中间结果加到累加器中以在累加器中产生打包累计结果。这些步骤可以用第一组值和第二组值的部分迭代到累加器，以产生打包的累积结果。随后，将累加器中的打包累积结果解包成第一结果，将第二结果与第一结果和第二结果相加在一起以产生累积结果。

2. 发明授权

US5793661A Method and apparatus for performing multiply and accumulate operations on packed data 失效
标题翻译：对打包数据执行乘法和累加操作的方法和装置
公开(公告)号：US5793661A
公开(公告)日：1998-08-11
申请号：US578827
申请日：1995-12-26
申请人： Carole Dulong , Larry Mennemeier , Tuan H. Bui , Eiichi Kowashi , Alexander D. Peleg , Benny Eitan , Stephen A. Fischer , Benny Maytal , Millind Mittal
发明人： Carole Dulong , Larry Mennemeier , Tuan H. Bui , Eiichi Kowashi , Alexander D. Peleg , Benny Eitan , Stephen A. Fischer , Benny Maytal , Millind Mittal
IPC分类号： G06F7/544 , G06F7/00
CPC分类号： G06F7/5443 , G06F2207/3828
摘要： A method of multiplying and accumulating two sets of values in a computer system. A packed multiply add is performed on a first portion of a first set of values packed into a first source and a first portion of a second set of values packed into a second source to generate a first result. The first result is unpacked into a plurality of values (e.g. two). The plurality of values is then added together to form a resulting accumulation value.
摘要翻译：一种在计算机系统中乘法和累加两组值的方法。在打包到第一源的第一组值的第一部分和打包到第二源中的第二组值的第一部分的第一部分上执行打包乘法加法以产生第一结果。第一个结果被打包成多个值（例如两个）。然后将多个值相加在一起以形成结果积累值。

3. 发明申请

US20120216018A1 PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA 失效
公开(公告)号：US20120216018A1
公开(公告)日：2012-08-23
申请号：US13456761
申请日：2012-04-26
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F15/76 , G06F9/302
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

4. 发明授权

US07509367B2 Method and apparatus for performing multiply-add operations on packed data 有权
公开(公告)号：US07509367B2
公开(公告)日：2009-03-24
申请号：US10861167
申请日：2004-06-04
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

5. 发明授权

US06385634B1 Method for performing multiply-add operations on packed data 失效
标题翻译：对打包数据进行乘法运算的方法
公开(公告)号：US06385634B1
公开(公告)日：2002-05-07
申请号：US08522067
申请日：1995-08-31
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F738
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

6. 发明申请

US20120331028A1 PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA 失效
标题翻译：用于在包装数据上执行多重添加操作的处理器
公开(公告)号：US20120331028A1
公开(公告)日：2012-12-27
申请号：US13603370
申请日：2012-09-04
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

7. 发明授权

US08185571B2 Processor for performing multiply-add operations on packed data 有权
标题翻译：用于对打包数据执行加法运算的处理器
公开(公告)号：US08185571B2
公开(公告)日：2012-05-22
申请号：US12409275
申请日：2009-03-23
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

8. 发明授权

US07424505B2 Method and apparatus for performing multiply-add operations on packed data 有权
公开(公告)号：US07424505B2
公开(公告)日：2008-09-09
申请号：US09989736
申请日：2001-11-19
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

9. 发明授权

US5984515A Computer implemented method for providing a two dimensional rotation of packed data 失效
标题翻译：用于提供打包数据的二维旋转的计算机实现的方法
公开(公告)号：US5984515A
公开(公告)日：1999-11-16
申请号：US917671
申请日：1997-08-21
申请人： Larry M. Mennemeier , Alexander D. Peleg , Carole Dulong , Eiichi Kowashi , Millind Mittal , Benny Eitan
发明人： Larry M. Mennemeier , Alexander D. Peleg , Carole Dulong , Eiichi Kowashi , Millind Mittal , Benny Eitan
IPC分类号： G06F9/302 , G06T3/60 , G06F17/14
CPC分类号： G06F9/30014 , G06F9/30036 , G06T3/60
摘要： In a computer system having stored therein a first and a second packed data having corresponding data elements, a method for generating a two dimensional rotation of said packed data. The method includes the steps of generating a first set of intermediate results in response to a first instruction by multiplying the data elements of the first packed data with corresponding elements of a third packed data. The elements of said third packed data represent either a sine or cosine function. A second step of generating a second set of intermediate results in response to a second instruction by multiplying the data elements of the second packed data with corresponding elements of a fourth packed data. The elements of the fourth packed data represent either a sine or cosine function. A third and final step of generating a set of final results in response to a third instruction by performing an arithmetic operation between corresponding elements of the first and second sets of intermediate results. The final results represent a two dimensional rotation of the elements of the first set of packed data.
摘要翻译：在其中存储有具有相应数据元素的第一和第二打包数据的计算机系统中，一种用于产生所述打包数据的二维旋转的方法。该方法包括以下步骤：通过将第一打包数据的数据元素与第三打包数据的相应元素相乘来响应于第一指令来生成第一组中间结果。所述第三打包数据的元素表示正弦或余弦函数。第二步骤，通过将第二打包数据的数据元素与第四打包数据的对应元素相乘来响应于第二指令来生成第二组中间结果。第四打包数据的元素表示正弦或余弦函数。通过在第一和第二组中间结果的相应元素之间执行算术运算来产生响应于第三指令的一组最终结果的第三和最后一步骤。最终结果表示第一组打包数据的元素的二维旋转。

10. 发明授权

US5935240A Computer implemented method for transferring packed data between register files and memory 失效
标题翻译：用于在寄存器文件和存储器之间传送打包数据的计算机实现的方法
公开(公告)号：US5935240A
公开(公告)日：1999-08-10
申请号：US573238
申请日：1995-12-15
申请人： Larry M. Mennemeier , Alexander D. Peleg , Andrew F. Glew , Carole Dulong , Eiichi Kowashi , Millind Mittal , Wolf Witt , Benny Eitan
发明人： Larry M. Mennemeier , Alexander D. Peleg , Andrew F. Glew , Carole Dulong , Eiichi Kowashi , Millind Mittal , Wolf Witt , Benny Eitan
IPC分类号： G06F13/16 , G06F9/305
CPC分类号： G06F13/16
摘要： A method for transferring packed data including the steps of first receiving an instruction from a set of instructions for transferring packed data between an extended register file and either an integer register file or a memory. In one embodiment, the extended register file includes eight registers, with each of the extended register storing up to sixty-four data bits. The integer register file also includes eight registers. The instruction includes an opcode that specifies a direction of the transfer with respect to the extended register file. The instructions are encoded in an instruction format having up to three bits addressing a destination operand and up to three bits addressing a source operand. The instruction is then translated to determine a direction of the transfer, a size of said packed data to be transferred, the address of the destination operand, and the address of the source operand. The instruction decoded by a decoder unit previously designed to decode the instruction format used to encode the set of instructions. In response to receiving the instruction, the packed data is transferred between the extended register file and either the integer register file or the memory, pursuant to the specifications of the translated instruction.
摘要翻译：一种用于传送打包数据的方法，包括以下步骤：首先从扩展寄存器文件和整数寄存器文件或存储器之间传送打包数据的一组指令接收指令。在一个实施例中，扩展寄存器文件包括八个寄存器，每个扩展寄存器最多存储64个数据位。整数寄存器文件还包括八个寄存器。该指令包括指定关于扩展寄存器文件的传送方向的操作码。指令以指令格式进行编码，最多三位寻址目标操作数，最多三位寻址源操作数。然后转换该指令以确定传送的方向，要传送的所述打包数据的大小，目的地操作数的地址和源操作数的地址。由解码器单元解码的指令，其先前设计为解码用于编码指令集的指令格式。响应于接收到该指令，根据翻译指令的规范，打包数据在扩展寄存器文件和整数寄存器文件或存储器之间传送。

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