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1. 发明申请

US20100052065A1 NEW METHOD FOR MECHANICAL STRESS ENHANCEMENT IN SEMICONDUCTOR DEVICES 有权
标题翻译：用于半导体器件中的机械应力增强的新方法
公开(公告)号：US20100052065A1
公开(公告)日：2010-03-04
申请号：US12391821
申请日：2009-02-24
申请人： Carlos H. Diaz , Yi-Ming Sheu , Anson Wang , Kong-Beng Thei , Sheng-Chen Chung , Hao-Yi Tsai , Hsien-Wei Chen , Harry Hak-Lay Chuang , Shin-Puu Jeng
发明人： Carlos H. Diaz , Yi-Ming Sheu , Anson Wang , Kong-Beng Thei , Sheng-Chen Chung , Hao-Yi Tsai , Hsien-Wei Chen , Harry Hak-Lay Chuang , Shin-Puu Jeng
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823828 , H01L27/0207 , H01L29/165 , H01L29/66628 , H01L29/7848
摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having an active region; at least one operational device on the active region, wherein the operational device include a strained channel; and at least one first dummy gate disposed at a side of the operational device and on the active region.
摘要翻译：本发明提供集成电路。集成电路包括具有有源区的半导体衬底; 所述活动区域上的至少一个操作装置，其中所述操作装置包括应变通道; 以及设置在所述操作装置的一侧和所述有源区域上的至少一个第一伪栅极。

2. 发明授权

US09349655B2 Method for mechanical stress enhancement in semiconductor devices 有权
标题翻译：半导体器件中的机械应力增强方法
公开(公告)号：US09349655B2
公开(公告)日：2016-05-24
申请号：US12391821
申请日：2009-02-24
申请人： Carlos H. Diaz , Yi-Ming Sheu , Anson Wang , Kong-Beng Thei , Sheng-Chen Chung , Hao-Yi Tsai , Hsien-Wei Chen , Harry Hak-Lay Chuang , Shin-Puu Jeng
发明人： Carlos H. Diaz , Yi-Ming Sheu , Anson Wang , Kong-Beng Thei , Sheng-Chen Chung , Hao-Yi Tsai , Hsien-Wei Chen , Harry Hak-Lay Chuang , Shin-Puu Jeng
IPC分类号： H01L21/70 , H01L21/8238 , H01L27/02 , H01L29/165 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823828 , H01L27/0207 , H01L29/165 , H01L29/66628 , H01L29/7848
摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having an active region; at least one operational device on the active region, wherein the operational device include a strained channel; and at least one first dummy gate disposed at a side of the operational device and on the active region.
摘要翻译：本发明提供集成电路。集成电路包括具有有源区的半导体衬底; 所述活动区域上的至少一个操作装置，其中所述操作装置包括应变通道; 以及设置在所述操作装置的一侧和所述有源区域上的至少一个第一伪栅极。

3. 发明授权

US08334582B2 Protective seal ring for preventing die-saw induced stress 有权
标题翻译：用于防止模锯引起的应力的保护密封环
公开(公告)号：US08334582B2
公开(公告)日：2012-12-18
申请号：US12347026
申请日：2008-12-31
申请人： Shin-Puu Jeng , Hsien-Wei Chen , Shang-Yun Hou , Hao-Yi Tsai , Anbiarshy N. F. Wu , Yu-Wen Liu
发明人： Shin-Puu Jeng , Hsien-Wei Chen , Shang-Yun Hou , Hao-Yi Tsai , Anbiarshy N. F. Wu , Yu-Wen Liu
IPC分类号： H01L23/544
CPC分类号： H01L21/78 , H01L23/562 , H01L23/564 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip includes a semiconductor substrate; a plurality of low-k dielectric layers over the semiconductor substrate; a first passivation layer over the plurality of low-k dielectric layers; and a second passivation layer over the first passivation layer. A first seal ring is adjacent to an edge of the semiconductor chip, wherein the first seal ring has an upper surface substantially level to a bottom surface of the first passivation layer. A second seal ring is adjacent to the first seal ring and on an inner side of the semiconductor chip than the first seal ring. The second seal ring includes a pad ring in the first passivation layer and the second passivation layer. A trench ring includes at least a portion directly over the first seal ring. The trench ring extends from a top surface of the second passivation layer down to at least an interface between the first passivation layer and the second passivation layer.
摘要翻译：半导体芯片包括半导体衬底; 半导体衬底上的多个低k电介质层; 在所述多个低k电介质层上的第一钝化层; 以及在所述第一钝化层上的第二钝化层。第一密封环邻近半导体芯片的边缘，其中第一密封环具有基本上平坦于第一钝化层的底表面的上表面。第二密封环与第一密封环相邻，并且在半导体芯片的内侧与第一密封环相邻。第二密封环包括在第一钝化层和第二钝化层中的焊盘环。沟槽环包括直接在第一密封环上的至少一部分。沟槽环从第二钝化层的顶表面延伸到至少第一钝化层和第二钝化层之间的界面。

4. 发明授权

US08278737B2 Structure for improving die saw quality 有权
标题翻译：提高模锯质量的结构
公开(公告)号：US08278737B2
公开(公告)日：2012-10-02
申请号：US12417394
申请日：2009-04-02
申请人： Hsien-Wei Chen , Hao-Yi Tsai , Ying-Ju Chen , Yu-Wen Liu , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Hao-Yi Tsai , Ying-Ju Chen , Yu-Wen Liu , Shin-Puu Jeng
IPC分类号： H01L21/00
CPC分类号： H01L21/78 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided that includes a semiconductor substrate, a plurality of dies formed on the semiconductor substrate, the plurality of dies being separated from one another by a first region extending along a first direction and a second region extending along a second direction different from the first direction, a dummy metal structure formed within a third region that includes a region defined by an intersection of the first region and the second region, a plurality of metal interconnection layers formed over the substrate, and a plurality of dielectric layers formed over the substrate. Each of the metal interconnection layers is disposed within each of the dielectric layers and a dielectric constant of at least one of the dielectric layers is less than about 2.6.
摘要翻译：提供了一种半导体器件，其包括半导体衬底，形成在半导体衬底上的多个管芯，所述多个管芯沿着第一方向延伸的第一区域彼此分离，并且沿着不同于第二方向的第二方向延伸的第二区域第一方向，形成在第三区域内的虚设金属结构，所述第三区域包括由所述第一区域和所述第二区域的交点限定的区域，形成在所述基板上的多个金属互连层，以及形成在所述第二区域上的多个电介质层基质。每个金属互连层设置在每个介电层内，并且至少一个电介质层的介电常数小于约2.6。

5. 发明授权

US08178980B2 Bond pad structure 有权
标题翻译：焊盘结构
公开(公告)号：US08178980B2
公开(公告)日：2012-05-15
申请号：US12026312
申请日：2008-02-05
申请人： Shin-Puu Jeng , Yu-Wen Liu , Hao-Yi Tsai , Hsien-Wei Chen
发明人： Shin-Puu Jeng , Yu-Wen Liu , Hao-Yi Tsai , Hsien-Wei Chen
IPC分类号： H01L29/40
CPC分类号： H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/0401 , H01L2224/05093 , H01L2224/05096 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05187 , H01L2224/05552 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/16 , H01L2224/85201 , H01L2224/85205 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01049 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01087 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/30105 , H01L2924/3011 , H01L2924/37001 , H01L2924/00012 , H01L2924/00
摘要： A bonding pad structure is provided that includes two conductive layers and a connective layer interposing the two conductive layers. The connective layer includes a contiguous, conductive structure. In an embodiment, the contiguous conductive structure is a solid layer of conductive material. In other embodiments, the contiguous conductive structure is a conductive network including, for example, a matrix configuration or a plurality of conductive stripes. At least one dielectric spacer may interpose the conductive network. In an embodiment, the conductive density of the connective layer is between approximately 20% and 100%.
摘要翻译：提供了一种焊盘结构，其包括两个导电层和插入两个导电层的连接层。连接层包括连续的导电结构。在一个实施例中，邻接的导电结构是导电材料的固体层。在其它实施例中，连续导电结构是包括例如矩阵配置或多个导电条纹的导电网络。至少一个电介质间隔物可以插入导电网络。在一个实施例中，连接层的导电密度在大约20％和100％之间。

6. 发明申请

US20100117080A1 SEMICONDUCTOR TEST PAD STRUCTURES 有权
公开(公告)号：US20100117080A1
公开(公告)日：2010-05-13
申请号：US12267021
申请日：2008-11-07
申请人： Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
IPC分类号： H01L23/485
CPC分类号： H01L22/34 , H01L24/05 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer.
摘要翻译：具有集成的模具隔离保护屏障的半导体测试焊盘互连结构。互连结构包括多个堆叠的金属层，每个层具有通过介电材料层与其它测试焊盘分离的导电测试焊盘。在一个实施例中，至少一个金属通孔条被嵌入到互连结构中，并将金属层中的每个测试焊盘电连接在一起。在一些实施例中，通孔棒基本上沿着由每个测试垫限定的整个第一侧面延伸。在其他实施例中，可以提供一对相对的通孔条，其布置在限定在半导体晶片上的划线带中的模切单切锯切线的相对侧上。

7. 发明申请

US20090283911A1 Backend Interconnect Scheme with Middle Dielectric Layer Having Improved Strength 有权
标题翻译：后置互连方案与中间介质层具有改进的强度
公开(公告)号：US20090283911A1
公开(公告)日：2009-11-19
申请号：US12121541
申请日：2008-05-15
申请人： Hao-Yi Tsai , Yu-Wen Liu , Hsien-Wei Chen , Ying-Ju Chen , Shin-Puu Jeng
发明人： Hao-Yi Tsai , Yu-Wen Liu , Hsien-Wei Chen , Ying-Ju Chen , Shin-Puu Jeng
IPC分类号： H01L23/522
CPC分类号： H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L24/05 , H01L2224/02166 , H01L2224/05093 , H01L2224/05556 , H01L2924/14 , H01L2924/00
摘要： An integrated circuit structure includes a first, a second and a third metallization layer. The first metallization layer includes a first dielectric layer having a first k value; and first metal lines in the first dielectric layer. The second metallization layer is over the first metallization layer, and includes a second dielectric layer having a second k value greater than the first k value; and second metal lines in the second dielectric layer. The third metallization layer is over the second metallization layer, and includes a third dielectric layer having a third k value; and third metal lines in the third dielectric layer. The integrated circuit structure further includes a bottom passivation layer over the third metallization layer.
摘要翻译：集成电路结构包括第一，第二和第三金属化层。第一金属化层包括具有第一k值的第一介电层; 和第一介电层中的第一金属线。第二金属化层在第一金属化层之上，并且包括具有大于第一k值的第二k值的第二介电层; 和第二介电层中的第二金属线。第三金属化层在第二金属化层之上，并且包括具有第三k值的第三介电层; 和第三介电层中的第三金属线。集成电路结构还包括在第三金属化层上的底部钝化层。

8. 发明申请

US20080303539A1 Parametric testline with increased test pattern areas 有权
标题翻译：参数测试线具有增加的测试图案区域
公开(公告)号：US20080303539A1
公开(公告)日：2008-12-11
申请号：US11811135
申请日：2007-06-08
申请人： Hsien-Wei Chen , Shih-Hsun Hsu , Hao-Yi Tsai , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Shih-Hsun Hsu , Hao-Yi Tsai , Shin-Puu Jeng
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit parametric testline providing increased test pattern areas is disclosed. The testline comprises a dielectric layer over a substrate, a plurality of probe pads over the dielectric layer, and a first device under test (DUT) formed in the testline in a space underlying the probe pads. The testline may also include a second DUT, which is formed in a space underlying the probe pads overlying the first DUT in an overlaying configuration. The testline may further include a polygon shaped probe pad structure providing an increased test pattern area between adjacent probe pads.
摘要翻译：公开了一种提供增加的测试图案区域的集成电路参数测试线。测试线包括衬底上的电介质层，电介质层上的多个探针焊盘，以及形成在探针焊盘下方空间中的测试线中的第一被测器件（DUT）。测试线还可以包括第二DUT，其以覆盖配置形成在覆盖第一DUT的探针焊盘下方的空间中。测试线还可以包括多边形形状的探针焊盘结构，其提供相邻探针焊盘之间增加的测试图案区域。

9. 发明申请

US20080191205A1 Test structure for seal ring quality monitor 有权
标题翻译：密封圈质量监测仪的测试结构
公开(公告)号：US20080191205A1
公开(公告)日：2008-08-14
申请号：US11706940
申请日：2007-02-13
申请人： Hao-Yi Tsai , Shih-Hsun Hsu , Shih-Cheng Chang , Shang-Yun Hou , Hsien-Wei Chen , Chia-Lun Tsai , Benson Liu , Shin-Puu Jeng , Anbiarshy Wu
发明人： Hao-Yi Tsai , Shih-Hsun Hsu , Shih-Cheng Chang , Shang-Yun Hou , Hsien-Wei Chen , Chia-Lun Tsai , Benson Liu , Shin-Puu Jeng , Anbiarshy Wu
IPC分类号： H01L23/58
CPC分类号： H01L23/585 , H01L22/34 , H01L24/11 , H01L2224/0554 , H01L2224/05548 , H01L2224/05573 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05684 , H01L2224/45147 , H01L2224/48091 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor structure includes a daisy chain adjacent to an edge of a semiconductor chip. The daisy chain includes a plurality of horizontal metal lines distributed in a plurality of metallization layers, wherein the horizontal metal lines are serially connected; a plurality of connecting pads in a same layer and electrically connecting the horizontal metal lines, wherein the connecting pads are physically separated from each other; and a plurality of vertical metal lines, each connecting one of the connecting pads to one of the horizontal metal lines, wherein one of the plurality of connecting pads is connected to one of the plurality of horizontal metal lines by only one of the plurality of vertical metal lines; and a seal ring adjacent and electrically disconnected from the daisy chain.
摘要翻译：半导体结构包括与半导体芯片的边缘相邻的菊花链。菊花链包括分布在多个金属化层中的多个水平金属线，其中水平金属线串联连接; 在相同层中的多个连接焊盘并且电连接水平金属线，其中连接焊盘在物理上彼此分离; 以及多个垂直金属线，每个将所述连接焊盘中的一个连接到所述水平金属线之一，其中所述多个连接焊盘中的一个连接焊盘中的一个连接焊盘仅通过所述多个垂直金属线中的一个垂直连接金属线以及与菊花链相邻且电气断开的密封环。

10. 发明授权

US09859235B2 Underbump metallization structure 有权
公开(公告)号：US09859235B2
公开(公告)日：2018-01-02
申请号：US12619503
申请日：2009-11-16
申请人： Yu-Wen Liu , Hao-Yi Tsai , Hsien-Wei Chen , Shin-Puu Jeng , Ying-Ju Chen , Shang-Yun Hou , Pei-Haw Tsao , Chen-Hua Yu
发明人： Yu-Wen Liu , Hao-Yi Tsai , Hsien-Wei Chen , Shin-Puu Jeng , Ying-Ju Chen , Shang-Yun Hou , Pei-Haw Tsao , Chen-Hua Yu
IPC分类号： H01L23/488 , H01L23/00 , H01L23/31
CPC分类号： H01L24/05 , H01L23/3157 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/02125 , H01L2224/0215 , H01L2224/0345 , H01L2224/03462 , H01L2224/0401 , H01L2224/05018 , H01L2224/05027 , H01L2224/0508 , H01L2224/05096 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05541 , H01L2224/05552 , H01L2224/05553 , H01L2224/05557 , H01L2224/05558 , H01L2224/05566 , H01L2224/05569 , H01L2224/05572 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11462 , H01L2224/11849 , H01L2224/13005 , H01L2224/13007 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042 , H01L2924/05442 , H01L2924/00014 , H01L2924/2064 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599
摘要： A system and method for forming an underbump metallization (UBM) is presented. A preferred embodiment includes a raised UBM which extends through a passivation layer so as to make contact with a contact pad while retaining enough of the passivation layer between the contact pad and the UBM to adequately handle the peeling and shear stress that results from CTE mismatch and subsequent thermal processing. The UBM contact is preferably formed in either an octagonal ring shape or an array of contacts.

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