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1. 发明申请

US20210028289A1 TRENCH SPLIT-GATE DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
公开(公告)号：US20210028289A1
公开(公告)日：2021-01-28
申请号：US17041980
申请日：2019-03-27
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Dong FANG , Zheng BIAN
IPC分类号： H01L29/423 , H01L29/786 , H01L29/40 , H01L21/285
摘要： A method for manufacturing a trenched split-gate device, comprising: etching a semiconductor substrate to form a trench (120); depositing an oxide in the trench to form a floating-gate oxide layer in which the floating-gate oxide layer gradually thickens from top to bottom along a side wall of the trench, and a thickness of the floating gate oxide layer at a lower part of the side wall of the trench is the same as that of the floating gate oxide layer at a bottom of the trench; depositing polysilicon into the trench to form a floating-gate polysilicon layer (123); growing an insulation medium on an upper surface of the floating-gate polysilicon layer to form an isolation layer (124); and forming a control gate on the isolation layer in the trench.

2. 发明申请

US20210098606A1 VDMOS DEVICE AND MANUFACTURING METHOD THEREFOR 有权
公开(公告)号：US20210098606A1
公开(公告)日：2021-04-01
申请号：US17121360
申请日：2020-12-14
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Zheng BIAN
IPC分类号： H01L29/66 , H01L29/78 , H01L21/28 , H01L29/423
摘要： A VDMOS device and a manufacturing method therefor. The method comprises: forming a groove in a semiconductor substrate, wherein the groove comprises a first groove area, a second groove area and a third groove area communicating with the first groove area and the second groove area, and the width of the first groove area is greater than the widths of the second groove area and the third groove area; forming an insulation layer on the semiconductor substrate; forming a first polycrystalline silicon layer on the insulation layer; removing some of the first polycrystalline silicon layer; the first polycrystalline silicon layer forming in the first groove being used as a first electrode of a deep gate; removing all the insulation layer located on the surface of the semiconductor substrate and some of the insulation layer located in the groove; forming a gate oxide layer on the semiconductor substrate; forming a second polycrystalline silicon layer on the gate oxide layer; removing some of the second polycrystalline silicon layer; and the second polycrystalline silicon layer forming in the groove being used as a second electrode of a shallow gate.

3. 发明申请

US20190198665A1 VDMOS DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开
公开(公告)号：US20190198665A1
公开(公告)日：2019-06-27
申请号：US16329663
申请日：2017-08-09
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Zheng BIAN
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7813 , H01L29/66734 , H01L29/78
摘要： A VDMOS device and a manufacturing method therefor. The manufacturing method comprises: forming a groove in a semiconductor substrate, the groove comprising a first groove area, a second groove area, a third groove area, a fourth groove area and a fifth groove area; successively forming a first insulation layer, a first polycrystalline silicon layer and a second insulation layer on the semiconductor substrate; removing some of the second insulation layer until the first polycrystalline silicon layer is exposed; removing some of the first polycrystalline silicon layer, the remaining first polycrystalline silicon layer forming a first electrode; forming a third insulation layer on the semiconductor substrate, removing some of the third insulation layer, the second insulation layer and the first insulation layer, so that the top of the first polycrystalline silicon layer is higher than the top of the first insulation layer and the second insulation layer; and successively forming a gate oxide layer and a second polycrystalline silicon layer on the semiconductor substrate, and removing some of the second polycrystalline silicon layer, exposing the gate oxide layer located on the surface of the semiconductor substrate and the top of the second insulation layer, the remaining second polycrystalline silicon layer forming a second electrode.

4. 发明申请

US20190198644A1 VDMOS DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开
公开(公告)号：US20190198644A1
公开(公告)日：2019-06-27
申请号：US16329656
申请日：2017-08-09
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Zheng BIAN
IPC分类号： H01L29/66 , H01L29/423 , H01L29/78
CPC分类号： H01L29/66734 , H01L21/28 , H01L29/423 , H01L29/4236 , H01L29/78 , H01L29/7813 , H01L29/7831
摘要： A VDMOS device and a manufacturing method therefor. The method comprises: forming a groove in a semiconductor substrate, wherein the groove comprises a first groove area, a second groove area and a third groove area communicating with the first groove area and the second groove area, and the width of the first groove area is greater than the widths of the second groove area and the third groove area; forming an insulation layer on the semiconductor substrate; forming a first polycrystalline silicon layer on the insulation layer; removing some of the first polycrystalline silicon layer; the first polycrystalline silicon layer forming in the first groove being used as a first electrode of a deep gate; removing all the insulation layer located on the surface of the semiconductor substrate and some of the insulation layer located in the groove; forming a gate oxide layer on the semiconductor substrate; forming a second polycrystalline silicon layer on the gate oxide layer; removing some of the second polycrystalline silicon layer; and the second polycrystalline silicon layer forming in the groove being used as a second electrode of a shallow gate.

5. 发明申请

US20190027564A1 TRENCH GATE LEAD-OUT STRUCTURE AND MANUFACTURING METHOD THEREFOR 审中-公开
公开(公告)号：US20190027564A1
公开(公告)日：2019-01-24
申请号：US16064522
申请日：2017-05-26
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Zheng BIAN
IPC分类号： H01L29/423 , H01L29/78 , H01L29/06 , H01L29/66
摘要： A trench gate lead-out structure comprises a substrate (10), a trench formed in the surface of the substrate (10) and a first dielectric layer (22) on the substrate (10), and also comprises a polysilicon gate (31) at the inner surface of the trench. The trench is partially filled by the polysilicon gate (31), so that a recess exists in the trench above the polysilicon gate (31). A second dielectric layer (41) is filled in the recess. The trench gate lead-out structure also comprises a metal plug (50). The metal plug (50) downwards penetrates through the first dielectric layer (22) and then is inserted between the second dielectric layer (41) and the polysilicon gate (31), and accordingly is connected to the polysilicon gate (31).

6. 发明申请

US20180374925A1 TRENCH GATE STRUCTURE AND MANUFACTURING METHOD THEREFOR 审中-公开
公开(公告)号：US20180374925A1
公开(公告)日：2018-12-27
申请号：US16064550
申请日：2017-04-27
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Zheng BIAN
IPC分类号： H01L29/423 , H01L29/78 , H01L21/033 , H01L21/768 , H01L29/66
CPC分类号： H01L29/4236 , H01L21/0337 , H01L21/76897 , H01L29/42364 , H01L29/42376 , H01L29/4238 , H01L29/66704 , H01L29/66734 , H01L29/7813 , H01L29/7825
摘要： A trench gate structure and a manufacturing method therefor. The trench structure comprises a substrate (10), a trench on the surface of the substrate (10), an insulating spacer (20) on the substrate (10), a gate oxide layer (41) on the inner surface of the trench, and a polysilicon gate (40) on the gate oxide layer (41). The insulating spacer (20) abuts against the trench by means of a slope structure (21) of the insulating spacer; the polysilicon gate (40) extends onto the insulating spacer (20) along the slope structure (21) in the trench; the insulating spacer (20) comprises a polysilicon gate pull-up area (22) that is concave downwards with respect to other parts of the insulating spacer (20); the polysilicon gate (40) extending out of the trench is rested on the polysilicon gate pull-up area (22).

7. 发明公开

US20240322061A1 SINGLE-PHOTON AVALANCHE DIODE INTEGRATED WITH QUENCHING RESISTOR AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20240322061A1
公开(公告)日：2024-09-26
申请号：US18578226
申请日：2022-12-13
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Zheng BIAN , Kui XIAO , Aifeng ZHAO , Jinjie HU , Tao YANG
IPC分类号： H01L31/107 , H01L27/144 , H01L31/0216 , H01L31/18
CPC分类号： H01L31/107 , H01L27/1443 , H01L28/20 , H01L31/02164 , H01L31/1804
摘要： The present disclosure relates to a single-photon avalanche diode integrated with a quenching resistor and a manufacturing method thereof. The method includes: obtaining a wafer; patterning and etching a front surface of the base to form a quenching resistor trench and an isolation trench, wherein a width of the isolation trench is greater than a width of the quenching resistor trench; forming an insulation layer on an inner surface of the quenching resistor trench; depositing polycrystalline silicon on the front surface of the base, where the polycrystalline silicon is filled into the quenching resistor trench and seals the quenching resistor trench while the polycrystalline silicon is filled into the isolation trench and does not seal the isolation trench; performing oxidation treatment on the polycrystalline silicon in the isolation trench; filling a light-shielding conductive material into the isolation trench.

8. 发明申请

US20180277532A1 SEMICONDUCTOR DEVICE HAVING ELECTRO-STATIC DISCHARGE PROTECTION STRUCTURE 审中-公开
公开(公告)号：US20180277532A1
公开(公告)日：2018-09-27
申请号：US15764394
申请日：2016-08-24
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Zheng BIAN
IPC分类号： H01L27/02
CPC分类号： H01L27/0255 , H01L27/0629 , H01L29/0657 , H01L29/16 , H01L29/7801 , H01L29/866
摘要： A semiconductor device, having an electro-static discharge (ESD) protection structure, comprises: a diode, connected between a gate and a source of the semiconductor device, and comprising a diode main body, and two connection portions, respectively connected to two terminals of the diode main body and respectively electrically connected to the gate and the source; and a substrate comprising two insulation pads disposed thereon and separated from each other. A surface of the substrate between the insulation pads is provided with an insulation layer. The diode main body is arranged on the insulation layer. The two connection portions are configured to extend, respectively, from either end of the diode main body to the insulation pad on the corresponding side. A dielectric layer is arranged on the diode and the two insulation pads, and a metal conduction line layer is arranged on the dielectric layer.

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