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1. 发明授权

US07668007B2 Memory system including a resistance variable memory device 有权
标题翻译：存储器系统包括电阻变量存储器件
公开(公告)号：US07668007B2
公开(公告)日：2010-02-23
申请号：US12124523
申请日：2008-05-21
申请人： Byung-Gil Choi , Woo-Yeong Cho , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
发明人： Byung-Gil Choi , Woo-Yeong Cho , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2213/72
摘要： A memory system includes a resistance variable memory device, and a memory controller for controlling the resistance variable memory device. The resistance variable memory device includes a memory cell connected to a bitline, a high voltage circuit adapted to generate a high voltage from an externally provided power source voltage, where the high voltage is higher than the power source voltage, a precharging circuit adapted to charge the bitline to the power source voltage and further charge the bitline to the high voltage, a bias circuit adapted to provide a read current to the bitline with using the high voltage, and a sense amplifier adapted to detect a voltage level of the bitline with using the high voltage.
摘要翻译：存储器系统包括电阻可变存储器件和用于控制电阻变化存储器件的存储器控制器。电阻可变存储器件包括连接到位线的存储单元，适于从外部提供的电源电压产生高电压的高压电路，其中高电压高于电源电压，预充电电路适于充电位线到电源电压并进一步将位线充电到高电压，偏置电路适于使用高电压向位线提供读取电流;以及读出放大器，其适于使用来检测位线的电压电平高电压。

2. 发明申请

US20080232161A1 RESISTANCE VARIABLE MEMORY DEVICE AND READ METHOD THEREOF 有权
标题翻译：电阻可变存储器件及其读取方法
公开(公告)号：US20080232161A1
公开(公告)日：2008-09-25
申请号：US12124523
申请日：2008-05-21
申请人： Byung-Gil Choi , Woo-Yeong Cho , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
发明人： Byung-Gil Choi , Woo-Yeong Cho , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2213/72
摘要： A memory system includes a resistance variable memory device, and a memory controller for controlling the resistance variable memory device. The resistance variable memory device includes a memory cell connected to a bitline, a high voltage circuit adapted to generate a high voltage from an externally provided power source voltage, where the high voltage is higher than the power source voltage, a precharging circuit adapted to charge the bitline to the power source voltage and further charge the bitline to the high voltage, a bias circuit adapted to provide a read current to the bitline with using the high voltage, and a sense amplifier adapted to detect a voltage level of the bitline with using the high voltage.
摘要翻译：存储器系统包括电阻可变存储器件和用于控制电阻变化存储器件的存储器控制器。电阻可变存储器件包括连接到位线的存储单元，适于从外部提供的电源电压产生高电压的高压电路，其中高电压高于电源电压，预充电电路适于充电位线到电源电压并进一步将位线充电到高电压，偏置电路适于使用高电压向位线提供读取电流;以及读出放大器，其适于使用来检测位线的电压电平高电压。

3. 发明授权

US07391644B2 Phase-changeable memory device and read method thereof 有权
标题翻译：相变存储器件及其读取方法
公开(公告)号：US07391644B2
公开(公告)日：2008-06-24
申请号：US11605212
申请日：2006-11-29
申请人： Woo-Yeong Cho , Byung-Gil Choi , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
发明人： Woo-Yeong Cho , Byung-Gil Choi , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2213/72
摘要： Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.
摘要翻译：公开了一种可变相存储器件和读取数据的相关方法。存储器件包括存储器单元，高压电路，预充电电路，偏置电路和读出放大器。每个存储单元包括相位可变材料和连接到位线的二极管。高压电路从电源提供高电压。预充电电路将位线充电至电源电压后，将位线升高至高电压。偏置电路通过高电压向位线提供读取电流。读出放大器通过高电压将位线的电压与参考电压进行比较，并从存储单元读取数据。存储器件能够减少在预充电操作期间对高压电路的负担，从而在感测操作期间确保足够的感测余量。

4. 发明申请

US20070133271A1 Phase-changeable memory device and read method thereof 有权
标题翻译：相变存储器件及其读取方法
公开(公告)号：US20070133271A1
公开(公告)日：2007-06-14
申请号：US11605212
申请日：2006-11-29
申请人： Woo-Yeong Cho , Byung-Gil Choi , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
发明人： Woo-Yeong Cho , Byung-Gil Choi , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2213/72
摘要： Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.
摘要翻译：公开了一种可变相存储器件和读取数据的相关方法。存储器件包括存储器单元，高压电路，预充电电路，偏置电路和读出放大器。每个存储单元包括相位可变材料和连接到位线的二极管。高压电路从电源提供高电压。预充电电路将位线充电至电源电压后，将位线升高至高电压。偏置电路通过高电压向位线提供读取电流。读出放大器通过高电压将位线的电压与参考电压进行比较，并从存储单元读取数据。存储器件能够减少在预充电操作期间对高压电路的负担，从而在感测操作期间确保足够的感测余量。

5. 发明授权

US07499316B2 Phase change memory devices and program methods 有权
标题翻译：相变存储器件和程序方法
公开(公告)号：US07499316B2
公开(公告)日：2009-03-03
申请号：US11723354
申请日：2007-03-19
申请人： Byung-Gil Choi , Du-Eung Kim , Yu-Hwan Ro , Joon-Yong Choi , Beak-Hyung Cho , Woo-Yeong Cho
发明人： Byung-Gil Choi , Du-Eung Kim , Yu-Hwan Ro , Joon-Yong Choi , Beak-Hyung Cho , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2213/72
摘要： A phase change memory device is disclosed. It includes a memory cell array including a plurality of memory cells programmed in relation to a phase change material, and a write driver circuit configured to provide a set current and a reset current to a selected memory cell. The write driver circuit includes a set current driver configured to provide the set current and a reset current driver configured to provide the reset current.
摘要翻译：公开了一种相变存储器件。其包括存储单元阵列，其包括相对于相变材料编程的多个存储器单元，以及写入驱动器电路，其被配置为向所选存储单元提供置位电流和复位电流。写驱动器电路包括配置成提供设定电流的设定电流驱动器和被配置为提供复位电流的复位电流驱动器。

6. 发明申请

US20070230239A1 Phase change memory devices and program methods 有权
标题翻译：相变存储器件和程序方法
公开(公告)号：US20070230239A1
公开(公告)日：2007-10-04
申请号：US11723354
申请日：2007-03-19
申请人： Byung-Gil Choi , Du-Eung Kim , Yu-Hwan Ro , Joon-Yong Choi , Beak-Hyung Cho , Woo-Yeong Cho
发明人： Byung-Gil Choi , Du-Eung Kim , Yu-Hwan Ro , Joon-Yong Choi , Beak-Hyung Cho , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2213/72
摘要： A phase change memory device is disclosed. It includes a memory cell array including a plurality of memory cells programmed in relation to a phase change material, and a write driver circuit configured to provide a set current and a reset current to a selected memory cell. The write driver circuit includes a set current driver configured to provide the set current and a reset current driver configured to provide the reset current.
摘要翻译：公开了一种相变存储器件。其包括存储单元阵列，其包括相对于相变材料编程的多个存储器单元，以及写入驱动器电路，其被配置为向所选存储单元提供置位电流和复位电流。写驱动器电路包括配置成提供设定电流的设定电流驱动器和被配置为提供复位电流的复位电流驱动器。

7. 发明申请

US20070103972A1 Non-volatile phase-change memory device and method of reading the same 有权
标题翻译：非易失性相变存储器件及其读取方法
公开(公告)号：US20070103972A1
公开(公告)日：2007-05-10
申请号：US11316017
申请日：2005-12-23
申请人： Yu-Hwan Ro , Woo-Yeong Cho , Byung-Gil Choi
发明人： Yu-Hwan Ro , Woo-Yeong Cho , Byung-Gil Choi
IPC分类号： G11C11/00
CPC分类号： G11C5/145 , G11C5/143 , G11C7/12 , G11C11/5678 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C2013/0057 , G11C2213/72
摘要： In one aspect, a non-volatile semiconductor memory device includes a phase phase-change memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of phase-change memory cells, where each the phase-change memory cells includes a phase-change resistive element and a diode connected in series between a word line and a bit line among the plurality of word lines and bit lines of the phase-change memory cell array. The memory device of this aspect further includes a sense node which is selectively connected to a bit line of the phase-change memory cell array, a boosting circuit which generates a boosted voltage which is greater than an internal power supply voltage, a pre-charge and biasing circuit which is driven by the boosted voltage to pre-charge and bias the sense node, and a sense amplifier connected to the sense node. The boosted voltage may be equal to or greater than a sum of the internal power supply voltage and a threshold voltage of the diode of each phase-change memory cell.
摘要翻译：一方面，一种非易失性半导体存储器件包括：相位相变存储单元阵列，包括多个字线，多个位线和多个相变存储器单元，其中每个相变存储器单元包括在相变存储单元阵列的多个字线和位线之间串联连接在字线和位线之间的相变电阻元件和二极管。该方面的存储装置还包括有选择地连接到相变存储单元阵列的位线的感测节点，产生大于内部电源电压的升压电压的升压电路，预充电以及由升压电压驱动以对感测节点进行预充电和偏置的偏置电路，以及连接到感测节点的读出放大器。升压电压可以等于或大于内部电源电压和每个相变存储单元的二极管的阈值电压之和。

8. 发明授权

US07885098B2 Non-volatile phase-change memory device and method of reading the same 有权
标题翻译：非易失性相变存储器件及其读取方法
公开(公告)号：US07885098B2
公开(公告)日：2011-02-08
申请号：US11316017
申请日：2005-12-23
申请人： Yu-Hwan Ro , Woo-Yeong Cho , Byung-Gil Choi
发明人： Yu-Hwan Ro , Woo-Yeong Cho , Byung-Gil Choi
IPC分类号： G11C11/00
CPC分类号： G11C5/145 , G11C5/143 , G11C7/12 , G11C11/5678 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C2013/0057 , G11C2213/72
摘要： In one aspect, a non-volatile semiconductor memory device includes a phase phase-change memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of phase-change memory cells, where each the phase-change memory cells includes a phase-change resistive element and a diode connected in series between a word line and a bit line among the plurality of word lines and bit lines of the phase-change memory cell array. The memory device of this aspect further includes a sense node which is selectively connected to a bit line of the phase-change memory cell array, a boosting circuit which generates a boosted voltage which is greater than an internal power supply voltage, a pre-charge and biasing circuit which is driven by the boosted voltage to pre-charge and bias the sense node, and a sense amplifier connected to the sense node. The boosted voltage may be equal to or greater than a sum of the internal power supply voltage and a threshold voltage of the diode of each phase-change memory cell.
摘要翻译：一方面，一种非易失性半导体存储器件包括：相位相变存储单元阵列，包括多个字线，多个位线和多个相变存储器单元，其中每个相变存储器单元包括在相变存储单元阵列的多个字线和位线之间串联连接在字线和位线之间的相变电阻元件和二极管。该方面的存储装置还包括有选择地连接到相变存储单元阵列的位线的感测节点，产生大于内部电源电压的升压电压的升压电路，预充电以及由升压电压驱动以对感测节点进行预充电和偏置的偏置电路，以及连接到感测节点的读出放大器。升压电压可以等于或大于内部电源电压和每个相变存储单元的二极管的阈值电压之和。

9. 发明授权

US07817479B2 Nonvolatile memory device using a variable resistive element and associated operating method 有权
标题翻译：使用可变电阻元件和相关操作方法的非易失性存储器件
公开(公告)号：US07817479B2
公开(公告)日：2010-10-19
申请号：US12136822
申请日：2008-06-11
申请人： Yu-Hwan Ro , Byung-Gil Choi , In-Cheol Shin
发明人： Yu-Hwan Ro , Byung-Gil Choi , In-Cheol Shin
IPC分类号： G11C16/04
CPC分类号： G11C13/00 , G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/0078 , G11C2013/0092 , G11C2213/72
摘要： A nonvolatile memory device that utilizes both a voltage provided outside the memory device and a voltage generated within the device instead of using only a voltage generated within the device as a driving voltage avoids malfunctions of the memory device when instantaneous significant voltage drops occur. The nonvolatile memory device includes a plurality of nonvolatile memory cells, a bit line coupled to at least a portion of the plurality of nonvolatile memory cells, a column-selection transistor coupled to the bit line and a driving circuit. The driving circuit is coupled to a gate of the column-selection transistor and is configured to supply a charge to the gate using a first voltage and a second voltage wherein the second voltage is higher than the first voltage.
摘要翻译：使用提供在存储器件外部的电压和在器件内产生的电压而不是仅使用在器件内产生的电压作为驱动电压的非易失性存储器件避免了当出现瞬时显着电压下降时存储器件的故障。非易失性存储器件包括多个非易失性存储器单元，耦合到多个非易失性存储器单元的至少一部分的位线，耦合到位线的列选择晶体管和驱动电路。驱动电路耦合到列选择晶体管的栅极，并且被配置为使用其中第二电压高于第一电压的第一电压和第二电压向栅极提供电荷。

10. 发明授权

US08243542B2 Resistance variable memory devices and read methods thereof 有权
标题翻译：电阻变量存储器件及其读取方法
公开(公告)号：US08243542B2
公开(公告)日：2012-08-14
申请号：US12691769
申请日：2010-01-22
申请人： Junsoo Bae , Dueung Kim , Kwangjin Lee , Hyungrok Oh , Beakhyung Cho , Byunggil Choi , Woo-Yeong Cho , Yu-Hwan Ro
发明人： Junsoo Bae , Dueung Kim , Kwangjin Lee , Hyungrok Oh , Beakhyung Cho , Byunggil Choi , Woo-Yeong Cho , Yu-Hwan Ro
IPC分类号： G11C7/00
CPC分类号： G11C8/10 , G11C5/145 , G11C7/04 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0038 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0076 , G11C2013/0078 , G11C2213/72
摘要： A resistance-variable memory device includes memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell may, for example, include a resistance-variable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline using the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage.
摘要翻译：电阻可变存储器件包括存储单元，高压电路，预充电电路，偏置电路和读出放大器。每个存储单元可以例如包括电阻可变材料和连接到位线的二极管。高压电路从电源提供高电压。预充电电路将位线充电至电源电压后，将位线升高至高电压。偏置电路使用高电压向位线提供读取电流。读出放大器通过高电压将位线的电压与参考电压进行比较。

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