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1. 发明授权

US07863643B2 Memory cell device having vertical channel and double gate structure 有权
标题翻译：具有垂直沟道和双栅结构的存储单元器件
公开(公告)号：US07863643B2
公开(公告)日：2011-01-04
申请号：US12309959
申请日：2007-09-20
申请人： Byung Gook Park , Il Han Park
发明人： Byung Gook Park , Il Han Park
IPC分类号： H01L29/66
CPC分类号： H01L27/115 , H01L27/11568
摘要： A memory cell device having a vertical channel and a double gate structure is provided. More specifically, a memory cell device having a vertical channel and a double gate structure is characterized by having a pillar active region with a predetermined height, which is including a first semiconductor layer forming a first source/drain region, a second semiconductor layer being placed under the first semiconductor layer with a predetermined distance and forming a second source/drain region, and a third semiconductor layer forming a body region and a channel region between the first semiconductor layer and the second semiconductor layer, and therefore, there is no need for unnecessary contacts when it is used as a unit cell for any type of memory array, not to speak of NOR type flash memory array. And the present invention makes to program/erase more effectively and increase the read speed and the amount of sensing current.
摘要翻译：提供具有垂直通道和双栅极结构的存储单元器件。更具体地说，具有垂直沟道和双栅极结构的存储单元器件的特征在于具有预定高度的柱状有源区，其包括形成第一源极/漏极区的第一半导体层，放置第二半导体层的第二半导体层在第一半导体层之下具有预定距离并形成第二源极/漏极区域，以及形成第一半导体层和第二半导体层之间的体区域和沟道区域的第三半导体层，因此不需要当它被用作任何类型的存储器阵列的单位单元时，不用说NOR型闪存阵列就是不必要的接触。并且本发明使得更有效地编程/擦除并增加读取速度和感测电流的量。

2. 发明授权

US08766349B2 Semiconductor device having stacked array structure, NAND flash memory array using the same and fabrication thereof 有权
标题翻译：具有堆叠阵列结构的半导体器件，使用其的NAND闪存阵列及其制造
公开(公告)号：US08766349B2
公开(公告)日：2014-07-01
申请号：US13383097
申请日：2009-12-22
申请人： Byung Gook Park , Jang Gn Yun , Il Han Park
发明人： Byung Gook Park , Jang Gn Yun , Il Han Park
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11565 , H01L27/11578 , H01L27/11582
摘要： The present invention relates to a semiconductor device, a memory array and a fabrication method thereof, and more particularly to a semiconductor device having a stacked array structure (referred to as a STAR structure: a STacked ARray structure) applicable to not only a switch device but also a memory device, a NAND flash memory array using the same as a memory device and a fabrication method thereof.
摘要翻译：本发明涉及一种半导体器件，存储器阵列及其制造方法，更具体地说，涉及一种具有堆叠阵列结构（简称为STAR结构：堆叠式ARray结构）的半导体器件，其不仅适用于开关器件而且还包括使用与存储器件相同的存储器件，NAND闪存阵列及其制造方法。

3. 发明申请

US20120117316A1 SEMICONDUCTOR DEVICE HAVING STACKED ARRAY STRUCTURE, NAND FLASH MEMORY ARRAY USING THE SAME AND FABRICATION THEREOF 有权
标题翻译：具有堆叠阵列结构的半导体器件，使用其的NAND闪存存储器阵列及其制造方法
公开(公告)号：US20120117316A1
公开(公告)日：2012-05-10
申请号：US13383097
申请日：2009-12-22
申请人： Byung Gook Park , Jang Gn Yun , Il Han Park
发明人： Byung Gook Park , Jang Gn Yun , Il Han Park
IPC分类号： G06F12/02
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11565 , H01L27/11578 , H01L27/11582
摘要： The present invention relates to a semiconductor device, a memory array and a fabrication method thereof, and more particularly to a semiconductor device having a stacked array structure (referred to as a STAR structure: a STacked ARray structure) applicable to not only a switch device but also a memory device, a NAND flash memory array using the same as a memory device and a fabrication method thereof.
摘要翻译：本发明涉及一种半导体器件，存储器阵列及其制造方法，更具体地说，涉及一种具有堆叠阵列结构（简称为STAR结构：堆叠式ARray结构）的半导体器件，其不仅适用于开关器件而且还包括使用其作为存储器件的存储器件，NAND闪速存储器阵列及其制造方法。

4. 发明申请

US20170178740A1 NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME 有权
公开(公告)号：US20170178740A1
公开(公告)日：2017-06-22
申请号：US15381724
申请日：2016-12-16
申请人： Youngmin Kim , Il Han Park , Sung-Won Yun , Hyejin Yim
发明人： Youngmin Kim , Il Han Park , Sung-Won Yun , Hyejin Yim
IPC分类号： G11C16/34 , G11C16/08 , G11C16/10 , G11C11/56
CPC分类号： G11C16/3459 , G11C11/5671 , G11C16/08 , G11C16/10 , G11C16/3481 , G11C2211/562 , G11C2211/5621 , G11C2211/5644
摘要： A nonvolatile memory device is provided as follows. A memory cell array includes a plurality of memory cells. An address decoder provides a first verify voltage to selected memory cells among the plurality of memory cells in a first program loop and provides a second verify voltage to the selected memory cells in a second program loop. A control logic determines the second program loop as a verify voltage offset point in which the first verify voltage is changed to the second verify voltage based on a result of a verify operation of the first program loop.

5. 发明授权

US09257185B2 Nonvolatile memory device, nonvolatile memory system, program method thereof, and operation method of controller controlling the same 有权
标题翻译：非易失性存储器件，非易失性存储器系统，其程序方法和控制器的控制方法
公开(公告)号：US09257185B2
公开(公告)日：2016-02-09
申请号：US13618605
申请日：2012-09-14
申请人： Il Han Park , Yongsung Cho , Sang-Soo Park
发明人： Il Han Park , Yongsung Cho , Sang-Soo Park
IPC分类号： G11C16/10 , G11C16/24 , G11C16/34
CPC分类号： G11C16/10 , G11C16/24 , G11C16/3427
摘要： According to example embodiments, a nonvolatile memory device includes a first memory cell configured to store a first data pattern, a second memory cell configured to be programmed using a program voltage, and a coupling program control unit. The coupling program control unit may be configured to perform a verification operation for verifying whether the first memory cell is programmed with the first data pattern. The verification operation may provide to the first memory cell a verification voltage corresponding to the first data pattern. The coupling program control unit may be configured to end programming the second memory cell when the verification operation on the first memory cell indicates a pass.
摘要翻译：根据示例性实施例，非易失性存储器件包括被配置为存储第一数据模式的第一存储器单元，被配置为使用编程电压进行编程的第二存储器单元和耦合程序控制单元。耦合程序控制单元可以被配置为执行用于验证第一存储单元是否用第一数据模式编程的验证操作。验证操作可以向第一存储器单元提供对应于第一数据模式的验证电压。耦合程序控制单元可以被配置为当对第一存储器单元的验证操作指示通过时，结束对第二存储器单元的编程。

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