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1. 发明授权

US07863643B2 Memory cell device having vertical channel and double gate structure 有权
标题翻译：具有垂直沟道和双栅结构的存储单元器件
公开(公告)号：US07863643B2
公开(公告)日：2011-01-04
申请号：US12309959
申请日：2007-09-20
申请人： Byung Gook Park , Il Han Park
发明人： Byung Gook Park , Il Han Park
IPC分类号： H01L29/66
CPC分类号： H01L27/115 , H01L27/11568
摘要： A memory cell device having a vertical channel and a double gate structure is provided. More specifically, a memory cell device having a vertical channel and a double gate structure is characterized by having a pillar active region with a predetermined height, which is including a first semiconductor layer forming a first source/drain region, a second semiconductor layer being placed under the first semiconductor layer with a predetermined distance and forming a second source/drain region, and a third semiconductor layer forming a body region and a channel region between the first semiconductor layer and the second semiconductor layer, and therefore, there is no need for unnecessary contacts when it is used as a unit cell for any type of memory array, not to speak of NOR type flash memory array. And the present invention makes to program/erase more effectively and increase the read speed and the amount of sensing current.
摘要翻译：提供具有垂直通道和双栅极结构的存储单元器件。更具体地说，具有垂直沟道和双栅极结构的存储单元器件的特征在于具有预定高度的柱状有源区，其包括形成第一源极/漏极区的第一半导体层，放置第二半导体层的第二半导体层在第一半导体层之下具有预定距离并形成第二源极/漏极区域，以及形成第一半导体层和第二半导体层之间的体区域和沟道区域的第三半导体层，因此不需要当它被用作任何类型的存储器阵列的单位单元时，不用说NOR型闪存阵列就是不必要的接触。并且本发明使得更有效地编程/擦除并增加读取速度和感测电流的量。

2. 发明申请

US20180204624A1 NON-VOLATILE MEMORY DEVICE FOR READING DATA WITH OPTIMIZED READ VOLTAGE 审中-公开
公开(公告)号：US20180204624A1
公开(公告)日：2018-07-19
申请号：US15716404
申请日：2017-09-26
申请人： Hyun-jun YOON , Il-han PARK , Na-young CHOI , Seung-hwan SONG
发明人： Hyun-jun YOON , Il-han PARK , Na-young CHOI , Seung-hwan SONG
IPC分类号： G11C16/28 , G11C16/04
CPC分类号： G11C16/28 , G11C16/0458 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/30
摘要： Provided is a read method for a nonvolatile memory device for reading data with an optimum read voltage. The read method includes reading data of a first set of memory cells connected to a first word line, by dividing the data of the first set of memory cells into M pages and individually reading data from the M pages. The reading data includes performing an on-chip valley search (OVS) operation on a first valley of two adjacent threshold voltage distributions of the first set of memory cells when reading each of the M pages, and performing a data recover read operation via a read operation on a second word line adjacent to the first word line, based on a result of the OVS operation. In the data recover read operation, a read operation on the first word line is not performed.

3. 发明申请

US20170178740A1 NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME 有权
公开(公告)号：US20170178740A1
公开(公告)日：2017-06-22
申请号：US15381724
申请日：2016-12-16
申请人： Youngmin Kim , Il Han Park , Sung-Won Yun , Hyejin Yim
发明人： Youngmin Kim , Il Han Park , Sung-Won Yun , Hyejin Yim
IPC分类号： G11C16/34 , G11C16/08 , G11C16/10 , G11C11/56
CPC分类号： G11C16/3459 , G11C11/5671 , G11C16/08 , G11C16/10 , G11C16/3481 , G11C2211/562 , G11C2211/5621 , G11C2211/5644
摘要： A nonvolatile memory device is provided as follows. A memory cell array includes a plurality of memory cells. An address decoder provides a first verify voltage to selected memory cells among the plurality of memory cells in a first program loop and provides a second verify voltage to the selected memory cells in a second program loop. A control logic determines the second program loop as a verify voltage offset point in which the first verify voltage is changed to the second verify voltage based on a result of a verify operation of the first program loop.

4. 发明授权

US09257185B2 Nonvolatile memory device, nonvolatile memory system, program method thereof, and operation method of controller controlling the same 有权
标题翻译：非易失性存储器件，非易失性存储器系统，其程序方法和控制器的控制方法
公开(公告)号：US09257185B2
公开(公告)日：2016-02-09
申请号：US13618605
申请日：2012-09-14
申请人： Il Han Park , Yongsung Cho , Sang-Soo Park
发明人： Il Han Park , Yongsung Cho , Sang-Soo Park
IPC分类号： G11C16/10 , G11C16/24 , G11C16/34
CPC分类号： G11C16/10 , G11C16/24 , G11C16/3427
摘要： According to example embodiments, a nonvolatile memory device includes a first memory cell configured to store a first data pattern, a second memory cell configured to be programmed using a program voltage, and a coupling program control unit. The coupling program control unit may be configured to perform a verification operation for verifying whether the first memory cell is programmed with the first data pattern. The verification operation may provide to the first memory cell a verification voltage corresponding to the first data pattern. The coupling program control unit may be configured to end programming the second memory cell when the verification operation on the first memory cell indicates a pass.
摘要翻译：根据示例性实施例，非易失性存储器件包括被配置为存储第一数据模式的第一存储器单元，被配置为使用编程电压进行编程的第二存储器单元和耦合程序控制单元。耦合程序控制单元可以被配置为执行用于验证第一存储单元是否用第一数据模式编程的验证操作。验证操作可以向第一存储器单元提供对应于第一数据模式的验证电压。耦合程序控制单元可以被配置为当对第一存储器单元的验证操作指示通过时，结束对第二存储器单元的编程。

5. 发明申请

US20130336058A1 NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION 有权
标题翻译：非易失性存储器件及其相关操作方法
公开(公告)号：US20130336058A1
公开(公告)日：2013-12-19
申请号：US13795750
申请日：2013-03-12
申请人： SANG-HYUN JOO , IL-HAN PARK , KI-WHAN SONG
发明人： SANG-HYUN JOO , IL-HAN PARK , KI-WHAN SONG
IPC分类号： G11C16/34
CPC分类号： G11C16/3418 , G11C11/5628 , G11C16/06 , G11C16/10 , G11C16/26
摘要： A nonvolatile memory device comprises a nonvolatile memory chip comprising a static latch, first and second dynamic latches that receive the data stored in the static latch through a floating node, and a memory cell configured to store multi-bit data. The nonvolatile memory device performs a refresh operation on the first dynamic latch where externally supplied first single bit data is stored in the first dynamic latch, performs a refresh operation on the second dynamic latch where externally supplied second single bit data is stored in the second dynamic latch, and programs the memory cell using the data stored in the first and second dynamic latches after the first and second single bit data are stored in the respective first and second dynamic latches.
摘要翻译：非易失性存储器件包括非易失性存储器芯片，其包括静态锁存器，通过浮动节点接收存储在静态锁存器中的数据的第一和第二动态锁存器以及被配置为存储多位数据的存储器单元。非易失性存储器件对第一动态锁存器执行刷新操作，其中外部提供的第一单位数据被存储在第一动态锁存器中，对外部提供的第二单位数据存储在第二动态锁存器中的第二动态锁存器执行刷新操作在第一和第二单个位数据存储在相应的第一和第二动态锁存器中之后，使用存储在第一和第二动态锁存器中的数据对存储器单元进行锁存和编程。

6. 发明申请

US20120117316A1 SEMICONDUCTOR DEVICE HAVING STACKED ARRAY STRUCTURE, NAND FLASH MEMORY ARRAY USING THE SAME AND FABRICATION THEREOF 有权
标题翻译：具有堆叠阵列结构的半导体器件，使用其的NAND闪存存储器阵列及其制造方法
公开(公告)号：US20120117316A1
公开(公告)日：2012-05-10
申请号：US13383097
申请日：2009-12-22
申请人： Byung Gook Park , Jang Gn Yun , Il Han Park
发明人： Byung Gook Park , Jang Gn Yun , Il Han Park
IPC分类号： G06F12/02
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11565 , H01L27/11578 , H01L27/11582
摘要： The present invention relates to a semiconductor device, a memory array and a fabrication method thereof, and more particularly to a semiconductor device having a stacked array structure (referred to as a STAR structure: a STacked ARray structure) applicable to not only a switch device but also a memory device, a NAND flash memory array using the same as a memory device and a fabrication method thereof.
摘要翻译：本发明涉及一种半导体器件，存储器阵列及其制造方法，更具体地说，涉及一种具有堆叠阵列结构（简称为STAR结构：堆叠式ARray结构）的半导体器件，其不仅适用于开关器件而且还包括使用其作为存储器件的存储器件，NAND闪速存储器阵列及其制造方法。

7. 发明申请

US20080128757A1 Non-volatile memory devices including vertical channels, methods of operating, and methods of fabricating the same 有权
标题翻译：包括垂直通道的非易失性存储器件，操作方法及其制造方法
公开(公告)号：US20080128757A1
公开(公告)日：2008-06-05
申请号：US11999135
申请日：2007-12-04
申请人： Soo-Doo Chae , Chung-Woo Kim , Chan-Jin Park , Jeong-Hee Han , Byung-Gook Park , Il-Han Park
发明人： Soo-Doo Chae , Chung-Woo Kim , Chan-Jin Park , Jeong-Hee Han , Byung-Gook Park , Il-Han Park
IPC分类号： G11C11/407 , H01L29/788
CPC分类号： H01L27/115 , G11C16/0416 , H01L27/11521 , H01L27/11524 , H01L29/66825 , H01L29/7881
摘要： A flash memory device can include a semiconductor pin protruding from a semiconductor substrate of a first conductive type to extend in one direction, a first doped layer and a second doped layer provided to an upper portion and a lower portion of the semiconductor pin, respectively, to be vertically spaced apart from each other, the first and second doped layers having a second conductive type, and a plurality of word lines extending over a top and a sidewall of the semiconductor pin to intersect the direction. The word lines overlap the first doped layer and the second doped layer to have vertical channels.
摘要翻译：闪速存储器件可以包括从第一导电类型的半导体衬底突出以在一个方向上延伸的半导体引脚，分别设置到半导体引脚的上部和下部的第一掺杂层和第二掺杂层，彼此垂直间隔开，第一和第二掺杂层具有第二导电类型，并且多个字线在半导体引脚的顶部和侧壁上延伸以与该方向相交。字线与第一掺杂层和第二掺杂层重叠以具有垂直沟道。

8. 发明申请

US20060278927A1 BODY BIASING STRUCTURE OF SOI 有权
标题翻译： SOI的身体偏心结构
公开(公告)号：US20060278927A1
公开(公告)日：2006-12-14
申请号：US11423696
申请日：2006-06-12
申请人： Byung-Gook PARK , Tae-Hoon KIM , Il-Han PARK
发明人： Byung-Gook PARK , Tae-Hoon KIM , Il-Han PARK
IPC分类号： H01L27/12
CPC分类号： H01L29/78615
摘要： A body biasing structure of devices connected in series on an SOI substrate is provided. According to some embodiments, the shallow junction of common source/drain regions enables all devices to bias by only one body contact on an SOI substrate like a conventional bulk MOSFET, and the floating body effect on an SOI substrate can be prevented.
摘要翻译：提供了在SOI衬底上串联连接的器件的体偏置结构。根据一些实施例，公共源极/漏极区的浅结使得所有器件只能像SOI传统体MOSFET在SOI衬底上仅偏移一个体接触，并且可以防止在SOI衬底上的浮体效应。

9. 外观设计

USD511115S1 Lightning arrester 失效
公开(公告)号：USD511115S1
公开(公告)日：2005-11-01
申请号：US29211844
申请日：2004-08-24
申请人： Young-Ki Chung , Il-Han Park , Kang-Su Lee
设计人： Young-Ki Chung , Il-Han Park , Kang-Su Lee

10. 发明申请

US20050147435A1 Fusing device of an image forming apparatus and method thereof 有权
标题翻译：图像形成装置的定影装置及其方法
公开(公告)号：US20050147435A1
公开(公告)日：2005-07-07
申请号：US10960093
申请日：2004-10-08
申请人： In-gu Kwak , Il-han Park
发明人： In-gu Kwak , Il-han Park
IPC分类号： G03G15/20
CPC分类号： G03G15/2053 , G03G2215/2016 , G03G2215/2035
摘要： A fusing device of an image forming apparatus and method thereof are provided. The fusing device and method comprise a conductive member having a linear portion for contacting a printing medium; a fusing film for sliding on a circumference of the conductive member; a pressing roller for contacting the fusing film in the linear portion, forming a fusing nip area, and rotating the fusing film; and an induction heating unit for heating the conductive member by induction and generating heat, wherein the thickness of the conductive member in the fusing nip area is smaller than the thickness of the conductive member in other areas.
摘要翻译：提供了图像形成装置的定影装置及其方法。定影装置和方法包括具有用于接触打印介质的线性部分的导电构件; 用于在导电构件的圆周上滑动的定影膜; 用于使所述直线部分中的所述定影膜接触的加压辊，形成定影夹持区域并使所述定影膜旋转; 以及感应加热单元，用于通过感应和发热来加热导电构件，其中定影夹持区域中的导电构件的厚度小于其它区域中的导电构件的厚度。

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