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1. 发明授权

US07364977B2 Heterojunction bipolar transistor and method of fabricating the same 失效
标题翻译：异质结双极晶体管及其制造方法
公开(公告)号：US07364977B2
公开(公告)日：2008-04-29
申请号：US10857655
申请日：2004-05-28
申请人： Byoung-Gue Min , Kyung-Ho Lee , Seong-Il Kim , Jong-Min Lee , Chul-Won Ju
发明人： Byoung-Gue Min , Kyung-Ho Lee , Seong-Il Kim , Jong-Min Lee , Chul-Won Ju
IPC分类号： H01L21/8222
CPC分类号： H01L29/66318 , H01L29/7371
摘要： Disclosed are a heterojunction bipolar transistor and a method of fabricating the same. A first dielectric layer easily etched is deposited on the overall surface of a substrate before an isolation region is defined. The first dielectric layer and a sub-collector layer are selectively etched, and then a second dielectric layer etched at a low etch rate is deposited on the overall surface of the substrate. Via holes are formed in the first and second dielectric layers, and then the first dielectric layer is removed using a difference between etch characteristics of the first and second dielectric layers. Accordingly, a reduction in power gain, generated at the interface of a compound semiconductor and a dielectric insulating layer (the second dielectric layer), can be eliminated.
摘要翻译：公开了异质结双极晶体管及其制造方法。在限定隔离区之前，易于蚀刻的第一电介质层沉积在基板的整个表面上。选择性地蚀刻第一介电层和次集电极层，然后以低蚀刻速率蚀刻的第二电介质层沉积在基板的整个表面上。在第一和第二电介质层中形成通孔，然后使用第一和第二电介质层的蚀刻特性之间的差异去除第一介电层。因此，可以消除在化合物半导体和介电绝缘层（第二介电层）的界面处产生的功率增益的降低。

2. 发明申请

US20050133820A1 Heterojunction bipolar transistor and method of fabricating the same 失效
标题翻译：异质结双极晶体管及其制造方法
公开(公告)号：US20050133820A1
公开(公告)日：2005-06-23
申请号：US10857655
申请日：2004-05-28
申请人： Byoung-Gue Min , Kyung-Ho Lee , Seong-Il Kim , Jong-Min Lee , Chul-Won Ju
发明人： Byoung-Gue Min , Kyung-Ho Lee , Seong-Il Kim , Jong-Min Lee , Chul-Won Ju
IPC分类号： H01L21/331 , H01L29/737 , H01L29/739 , H01L21/8222 , H01L31/0328
CPC分类号： H01L29/66318 , H01L29/7371
摘要： Disclosed are a heterojunction bipolar transistor and a method of fabricating the same. A first dielectric layer easily etched is deposited on the overall surface of a substrate before an isolation region is defined. The first dielectric layer and a sub-collector layer are selectively etched, and then a second dielectric layer etched at a low etch rate is deposited on the overall surface of the substrate. Via holes are formed in the first and second dielectric layers, and then the first dielectric layer is removed using a difference between etch characteristics of the first and second dielectric layers. Accordingly, a reduction in power gain, generated at the interface of a compound semiconductor and a dielectric insulating layer (the second dielectric layer), can be eliminated.
摘要翻译：公开了异质结双极晶体管及其制造方法。在限定隔离区之前，易于蚀刻的第一电介质层沉积在基板的整个表面上。选择性地蚀刻第一介电层和次集电极层，然后以低蚀刻速率蚀刻的第二电介质层沉积在基板的整个表面上。在第一和第二电介质层中形成通孔，然后使用第一和第二电介质层的蚀刻特性之间的差异去除第一介电层。因此，可以消除在化合物半导体和介电绝缘层（第二介电层）的界面处产生的功率增益的降低。

3. 发明授权

US08722474B2 Semiconductor device including stepped gate electrode and fabrication method thereof 有权
标题翻译：包括阶梯式栅电极的半导体器件及其制造方法
公开(公告)号：US08722474B2
公开(公告)日：2014-05-13
申请号：US13592589
申请日：2012-08-23
申请人： Hyung Sup Yoon , Byoung-Gue Min , Jong Min Lee , Seong-Il Kim , Dong Min Kang , Ho Kyun Ahn , Jong-Won Lim , Jae Kyoung Mun , Eun Soo Nam
发明人： Hyung Sup Yoon , Byoung-Gue Min , Jong Min Lee , Seong-Il Kim , Dong Min Kang , Ho Kyun Ahn , Jong-Won Lim , Jae Kyoung Mun , Eun Soo Nam
IPC分类号： H01L21/338
CPC分类号： H01L29/0649 , H01L21/28593 , H01L29/402 , H01L29/42316 , H01L29/66462 , H01L29/7786
摘要： Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer.
摘要翻译：本发明公开了一种半导体器件，包括阶梯栅电极和制造该半导体器件的方法。根据本公开的示例性实施例的半导体器件包括：半导体衬底，其具有包括多个外延层的结构，并且包括形成在其最上部的肖特基层的一部分中的下切割区域; 顺序地形成在半导体衬底上的盖层，第一氮化物层和第二氮化物层，以形成台阶栅极绝缘层图案; 以及通过栅极绝缘层图案沉积耐热金属而形成的阶梯形栅电极，其中下切区域包括形成在栅电极和肖特基层之间的空腔。

4. 发明申请

US20110140825A1 INDUCTOR 有权
标题翻译：电感器
公开(公告)号：US20110140825A1
公开(公告)日：2011-06-16
申请号：US12968022
申请日：2010-12-14
申请人： Seong-il KIM , Jongmin Lee , Byoung-Gue Min , Hyung Sup Yoon , Hae Cheon Kim , Eun Soo Nam
发明人： Seong-il KIM , Jongmin Lee , Byoung-Gue Min , Hyung Sup Yoon , Hae Cheon Kim , Eun Soo Nam
IPC分类号： H01F27/30
CPC分类号： H01F17/0006 , H01F2017/0086 , H01L28/10
摘要： Provided is an inductor. The inductor includes a first to a fourth conductive terminals formed in one direction within a semiconductor substrate, a first conductive line formed on one side of the semiconductor substrate and electrically connected to the second and third conductive terminals interiorly positioned among the first to fourth conductive terminals, a second conductive line formed on the one side of the semiconductor substrate and electrically connected to the first and fourth conductive terminals exteriorly positioned among the first to fourth conductive terminals, and a third conductive line formed on the other side of the semiconductor substrate and electrically connected to the first and third conductive terminals among the first to fourth conductive terminals.
摘要翻译：提供一种电感器。电感器包括在半导体衬底内的一个方向上形成的第一至第四导电端子，形成在半导体衬底的一侧上的第一导电线，并且电连接到内部位于第一至第四导电端子之间的第二和第三导电端子形成在所述半导体衬底的一侧上并与外部位于所述第一至第四导电端子之间的所述第一和第四导电端子电连接的第二导电线，以及形成在所述半导体衬底的另一侧上并电连接的第三导电线连接到第一至第四导电端子中的第一和第三导电端子。

5. 发明授权

US08130041B2 Power amplifier device 有权
标题翻译：功率放大器装置
公开(公告)号：US08130041B2
公开(公告)日：2012-03-06
申请号：US12960153
申请日：2010-12-03
申请人： Seong-Il Kim , Jongmin Lee , Byoung-Gue Min , Hyung Sup Yoon , Hae Cheon Kim , Eun Soo Nam
发明人： Seong-Il Kim , Jongmin Lee , Byoung-Gue Min , Hyung Sup Yoon , Hae Cheon Kim , Eun Soo Nam
IPC分类号： H03F3/68
CPC分类号： H03F3/245 , H03F1/0261 , H03F1/52 , H03F3/19 , H03F3/211 , H03F2200/18 , H03F2200/451
摘要： Provided is a power amplifier device. The power amplifier device includes: a cutoff unit cutting off a direct current (DC) component of a signal delivered from a signal input terminal; a circuit protecting unit connected to the cutoff unit and stabilizing a signal delivered from the cutoff unit; and an amplification unit connected to the circuit protecting unit and amplifying a signal delivered from the circuit protecting unit, wherein the amplification unit comprises a plurality of transistors connected in parallel to the circuit protecting unit and the circuit protecting unit comprises resistors connected to between bases of the plurality of transistors.
摘要翻译：提供了一种功率放大器装置。功率放大器装置包括：切断单元，切断从信号输入端子发送的信号的直流（DC）分量; 连接到所述切断单元的电路保护单元，并且稳定从所述切断单元传送的信号; 以及放大单元，连接到所述电路保护单元并放大从所述电路保护单元传送的信号，其中所述放大单元包括与所述电路保护单元并联连接的多个晶体管，所述电路保护单元包括电阻器，多个晶体管。

6. 发明授权

US07986211B2 Inductor 有权
标题翻译：电感器
公开(公告)号：US07986211B2
公开(公告)日：2011-07-26
申请号：US12968022
申请日：2010-12-14
申请人： Seong-il Kim , Jongmin Lee , Byoung-Gue Min , Hyung Sup Yoon , Hae Cheon Kim , Eun Soo Nam
发明人： Seong-il Kim , Jongmin Lee , Byoung-Gue Min , Hyung Sup Yoon , Hae Cheon Kim , Eun Soo Nam
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F2017/0086 , H01L28/10
摘要： Provided is an inductor. The inductor includes a first to a fourth conductive terminals formed in one direction within a semiconductor substrate, a first conductive line formed on one side of the semiconductor substrate and electrically connected to the second and third conductive terminals interiorly positioned among the first to fourth conductive terminals, a second conductive line formed on the one side of the semiconductor substrate and electrically connected to the first and fourth conductive terminals exteriorly positioned among the first to fourth conductive terminals, and a third conductive line formed on the other side of the semiconductor substrate and electrically connected to the first and third conductive terminals among the first to fourth conductive terminals.
摘要翻译：提供一种电感器。电感器包括在半导体衬底内的一个方向上形成的第一至第四导电端子，形成在半导体衬底的一侧上的第一导电线，并且电连接到内部位于第一至第四导电端子之间的第二和第三导电端子形成在所述半导体衬底的一侧上并与外部位于所述第一至第四导电端子之间的所述第一和第四导电端子电连接的第二导电线，以及形成在所述半导体衬底的另一侧上并电连接的第三导电线连接到第一至第四导电端子中的第一和第三导电端子。

7. 发明申请

US20110133843A1 POWER AMPLIFIER DEVICE 有权
标题翻译：功率放大器器件
公开(公告)号：US20110133843A1
公开(公告)日：2011-06-09
申请号：US12960153
申请日：2010-12-03
申请人： Seong-Il KIM , Jongmin Lee , Byoung-Gue Min , Hyung Sup Yoon , Hae Cheon Kim , Eun Soo Nam
发明人： Seong-Il KIM , Jongmin Lee , Byoung-Gue Min , Hyung Sup Yoon , Hae Cheon Kim , Eun Soo Nam
IPC分类号： H03F3/68
CPC分类号： H03F3/245 , H03F1/0261 , H03F1/52 , H03F3/19 , H03F3/211 , H03F2200/18 , H03F2200/451
摘要： Provided is a power amplifier device. The power amplifier device includes: a cutoff unit cutting off a direct current (DC) component of a signal delivered from a signal input terminal; a circuit protecting unit connected to the cutoff unit and stabilizing a signal delivered from the cutoff unit; and an amplification unit connected to the circuit protecting unit and amplifying a signal delivered from the circuit protecting unit, wherein the amplification unit comprises a plurality of transistors connected in parallel to the circuit protecting unit and the circuit protecting unit comprises resistors connected to between bases of the plurality of transistors.
摘要翻译：提供了一种功率放大器装置。功率放大器装置包括：切断单元，切断从信号输入端子发送的信号的直流（DC）分量; 连接到所述切断单元的电路保护单元，并且稳定从所述切断单元传送的信号; 以及放大单元，连接到所述电路保护单元并放大从所述电路保护单元传递的信号，其中所述放大单元包括与所述电路保护单元并联连接的多个晶体管，所述电路保护单元包括电阻器，多个晶体管。

8. 发明授权

US08853821B2 Vertical capacitors and methods of forming the same 有权
标题翻译：垂直电容器及其形成方法
公开(公告)号：US08853821B2
公开(公告)日：2014-10-07
申请号：US13618873
申请日：2012-09-14
申请人： Seong-il Kim , Sang-Heung Lee , Jong-Won Lim , Hyung Sup Yoon , Jongmin Lee , Byoung-Gue Min , Jae Kyoung Mun , Eun Soo Nam
发明人： Seong-il Kim , Sang-Heung Lee , Jong-Won Lim , Hyung Sup Yoon , Jongmin Lee , Byoung-Gue Min , Jae Kyoung Mun , Eun Soo Nam
IPC分类号： H01L21/02
CPC分类号： H01L28/91 , H01L23/481 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： Provided are vertical capacitors and methods of forming the same. The formation of the vertical capacitor may include forming input and output electrodes on a top surface of a substrate, etching a bottom surface of the substrate to form via electrodes, and then, forming a dielectric layer between the via electrodes. As a result, a vertical capacitor with high capacitance can be provided in a small region of the substrate.
摘要翻译：提供垂直电容器及其形成方法。垂直电容器的形成可以包括在衬底的顶表面上形成输入和输出电极，蚀刻衬底的底表面以形成通孔电极，然后在通孔电极之间形成电介质层。结果，可以在基板的小区域中提供具有高电容的垂直电容器。

9. 发明申请

US20120098099A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120098099A1
公开(公告)日：2012-04-26
申请号：US13193670
申请日：2011-07-29
申请人： Jongmin LEE , Byoung-Gue Min , Seong-il Kim , Hyung Sup Yoon , Hae Cheon Kim , Eun Soo Nam
发明人： Jongmin LEE , Byoung-Gue Min , Seong-il Kim , Hyung Sup Yoon , Hae Cheon Kim , Eun Soo Nam
IPC分类号： H01L27/06 , H01L21/8222
CPC分类号： H01L27/0605 , H01L21/8252 , H01L29/732 , H01L29/93 , H03C1/36
摘要： Provided are a compound semiconductor device and a method of manufacturing the same. The semiconductor device includes: a substrate including a first region and a second region; a transistor including first to third conductive impurity layers stacked on the substrate of the first region; and a variable capacitance diode spaced apart from the transistor of the first region and including the first and second conductive impurity layers stacked on the substrate of the second region.
摘要翻译：提供一种化合物半导体器件及其制造方法。半导体器件包括：衬底，其包括第一区域和第二区域; 晶体管，包括堆叠在所述第一区域的所述衬底上的第一至第三导电杂质层; 以及与第一区域的晶体管间隔开并且包括堆叠在第二区域的衬底上的第一和第二导电杂质层的可变电容二极管。

10. 发明授权

US08124489B2 Monolithic microwave integrated circuit device and method of forming the same 失效
标题翻译：单片微波集成电路器件及其形成方法
公开(公告)号：US08124489B2
公开(公告)日：2012-02-28
申请号：US12832432
申请日：2010-07-08
申请人： Byoung-Gue Min , Jongmin Lee , Seong-Il Kim , Hyung Sup Yoon
发明人： Byoung-Gue Min , Jongmin Lee , Seong-Il Kim , Hyung Sup Yoon
IPC分类号： H01L21/331
CPC分类号： H01L29/66318 , H01L21/8252 , H01L27/0605 , H01L29/66204 , H01L29/7371 , H01L29/868
摘要： Provided are a monolithic microwave integrated circuit device and a method for forming the same. The method includes: forming an sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer on a Heterojunction Bipolar Transistor (HBT) region and a PIN diode region of a substrate; forming an emitter pattern and an emitter cap pattern in the HBT region and exposing the base layer by patterning the emitter layer and the emitter cap layer; and forming an intrinsic region by doping a portion of the collector layer of the PIN diode region with a first type impurity, the PIN diode region being spaced apart from the HBT region.
摘要翻译：提供了一种单片微波集成电路器件及其形成方法。该方法包括：在基底的异质结双极晶体管（HBT）区域和PIN二极管区域上形成子集电极层，集电极层，基极层，发射极层和发射极盖层; 在HBT区域中形成发射极图案和发射极盖图案，并通过图案化发射极层和发射极盖层而使基底层曝光; 并且通过用第一类型杂质掺杂PIN二极管区域的集电极层的一部分来形成本征区域，PIN二极管区域与HBT区域间隔开。

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