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1. 发明申请

US20050035343A1 Gate shorted to body thin film transistor, manufacturing method thereof, and display including the same 有权
标题翻译：栅极与体薄膜晶体管短路，其制造方法以及包括其的显示器
公开(公告)号：US20050035343A1
公开(公告)日：2005-02-17
申请号：US10910350
申请日：2004-08-04
申请人： Byoung-Deog Choi , Won-Sik Kim , Myeong-Seob So
发明人： Byoung-Deog Choi , Won-Sik Kim , Myeong-Seob So
IPC分类号： G09F9/30 , H01L27/12 , H01L27/32 , H01L29/78 , H01L29/786 , H01L29/06
CPC分类号： H01L29/78666 , H01L27/12 , H01L29/783 , H01L29/7841 , H01L29/78609 , H01L29/78675
摘要： A TFT including a gate metallic layer, a body layer doped with a dopant having a first polarity, a source layer and a drain layer doped with a dopant having a second polarity, a semiconductor layer formed between the source layer and the drain layer, and a contact coupling the gate metallic layer and the body layer.
摘要翻译：一种TFT，包括栅极金属层，掺杂有第一极性的掺杂剂的体层，掺杂有第二极性的掺杂剂的源极层和漏极层，形成在源极层和漏极层之间的半导体层，以及耦合栅极金属层和主体层的接触。

2. 发明授权

US08704305B2 Thin film transistor 有权
标题翻译：薄膜晶体管
公开(公告)号：US08704305B2
公开(公告)日：2014-04-22
申请号：US10959976
申请日：2004-10-08
申请人： Jae-Bon Koo , Byoung-Deog Choi , Myeong-Seob So , Won-Sik Kim
发明人： Jae-Bon Koo , Byoung-Deog Choi , Myeong-Seob So , Won-Sik Kim
IPC分类号： H01L27/01
CPC分类号： H01L29/78615
摘要： A thin film transistor of the present invention comprises, an active layer formed on an insulating substrate and having a channel region and source/drain regions; a gate electrode formed corresponding to the channel region of the active region; a body contact region separately formed with the source/drain regions in the active layer; source/drain electrodes each connected to the source/drain regions; and a conductive wiring for connecting the body contact region and the gate electrode.
摘要翻译：本发明的薄膜晶体管包括：形成在绝缘基板上并具有沟道区域和源极/漏极区域的有源层; 形成对应于所述有源区的沟道区的栅电极; 与所述有源层中的源极/漏极区域分开形成的体接触区域; 源极/漏极，各自连接到源极/漏极区; 以及用于连接体接触区域和栅电极的导电布线。

3. 发明授权

US07274036B2 Gate shorted to body thin film transistor, manufacturing method thereof, and display including the same 有权
标题翻译：栅极与体薄膜晶体管短路，其制造方法以及包括其的显示器
公开(公告)号：US07274036B2
公开(公告)日：2007-09-25
申请号：US10910350
申请日：2004-08-04
申请人： Byoung-Deog Choi , Won-Sik Kim , Myeong-Seob So
发明人： Byoung-Deog Choi , Won-Sik Kim , Myeong-Seob So
IPC分类号： H01L29/04 , H01L29/10 , H01L31/00 , H01L29/12 , H01L29/786 , H01L27/01 , H01L27/12
CPC分类号： H01L29/78666 , H01L27/12 , H01L29/783 , H01L29/7841 , H01L29/78609 , H01L29/78675
摘要： A TFT including a gate metallic layer, a body layer doped with a dopant having a first polarity, a source layer and a drain layer doped with a dopant having a second polarity, a semiconductor layer formed between the source layer and the drain layer, and a contact coupling the gate metallic layer and the body layer.
摘要翻译：一种TFT，包括栅极金属层，掺杂有第一极性的掺杂剂的体层，掺杂有第二极性的掺杂剂的源极层和漏极层，形成在源极层和漏极层之间的半导体层，以及耦合栅极金属层和主体层的接触。

4. 发明申请

US20050082530A1 Thin film transistor 有权
标题翻译：薄膜晶体管
公开(公告)号：US20050082530A1
公开(公告)日：2005-04-21
申请号：US10959976
申请日：2004-10-08
申请人： Jae-Bon Koo , Byoung-Deog Choi , Myeong-Seob So , Won-Sik Kim
发明人： Jae-Bon Koo , Byoung-Deog Choi , Myeong-Seob So , Won-Sik Kim
IPC分类号： H01L29/786 , H01L29/10
CPC分类号： H01L29/78615
摘要： A thin film transistor of the present invention comprises, an active layer formed on an insulating substrate and having a channel region and source/drain regions; a gate electrode formed corresponding to the channel region of the active region; a body contact region separately formed with the source/drain regions in the active layer; source/drain electrodes each connected to the source/drain regions; and a conductive wiring for connecting the body contact region and the gate electrode.
摘要翻译：本发明的薄膜晶体管包括：形成在绝缘基板上并具有沟道区域和源极/漏极区域的有源层; 形成对应于所述有源区的沟道区的栅电极; 与所述有源层中的源极/漏极区域分开形成的体接触区域; 源极/漏极，各自连接到源极/漏极区; 以及用于连接体接触区域和栅电极的导电布线。

5. 发明申请

US20070052022A1 Thin film transistor, method of fabricating the same, and a display device including the thin film transistor 有权
标题翻译：薄膜晶体管，其制造方法以及包括薄膜晶体管的显示装置
公开(公告)号：US20070052022A1
公开(公告)日：2007-03-08
申请号：US11509853
申请日：2006-08-25
申请人： Byoung-Keon Park , Byoung-Deog Choi , Myeong-Seob So
发明人： Byoung-Keon Park , Byoung-Deog Choi , Myeong-Seob So
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/42384 , H01L27/124 , H01L29/66757
摘要： A thin film transistor (TFT), a method of fabricating the same, and a display device including the TFT, are provided. In the TFT, a channel region is connected to a gate electrode so that the influence of a substrate bias is reduced or eliminated. Thus, the threshold voltage of the TFT is reduced, a subthreshold slope can be improved, and a large drain current can be obtained at a low gate voltage.
摘要翻译：提供薄膜晶体管（TFT），其制造方法以及包括TFT的显示装置。在TFT中，沟道区域连接到栅电极，从而减小或消除衬底偏置的影响。因此，TFT的阈值电压降低，可以提高亚阈值斜率，并且可以在低栅极电压下获得大的漏极电流。

6. 发明授权

US07834397B2 Thin film transistor, method of fabricating the same, and a display device including the thin film transistor 有权
标题翻译：薄膜晶体管，其制造方法以及包括薄膜晶体管的显示装置
公开(公告)号：US07834397B2
公开(公告)日：2010-11-16
申请号：US11509853
申请日：2006-08-25
申请人： Byoung-Keon Park , Byoung-Deog Choi , Myeong-Seob So
发明人： Byoung-Keon Park , Byoung-Deog Choi , Myeong-Seob So
IPC分类号： H01L27/12
CPC分类号： H01L29/42384 , H01L27/124 , H01L29/66757
摘要： A thin film transistor (TFT), a method of fabricating the same, and a display device including the TFT, are provided. In the TFT, a channel region is connected to a gate electrode so that the influence of a substrate bias is reduced or eliminated. Thus, the threshold voltage of the TFT is reduced, a subthreshold slope can be improved, and a large drain current can be obtained at a low gate voltage.
摘要翻译：提供薄膜晶体管（TFT），其制造方法以及包括TFT的显示装置。在TFT中，沟道区域连接到栅电极，从而减小或消除衬底偏置的影响。因此，TFT的阈值电压降低，可以提高亚阈值斜率，并且可以在低栅极电压下获得大的漏极电流。

7. 发明申请

US20050110017A1 TFT modulating threshold voltage and flat panel display having the same 审中-公开
标题翻译： TFT调制阈值电压和具有相同的平板显示器
公开(公告)号：US20050110017A1
公开(公告)日：2005-05-26
申请号：US10992086
申请日：2004-11-19
申请人： Myeong-Seob So , Byoung-Deog Choi
发明人： Myeong-Seob So , Byoung-Deog Choi
IPC分类号： G02F1/1368 , H01L21/77 , H01L27/108 , H01L27/12 , H01L29/49 , H01L29/786
CPC分类号： H01L27/1214 , H01L29/4908 , H01L29/78609
摘要： The invention is directed to a thin film transistor (TFT) that modulates a threshold voltage in a simple manner. In one embodiment a TFT of the present invention also reduces a leakage current in an off state, and guarantees a sufficient threshold voltage margin and a flat panel display having the same are provided. The TFT includes a semiconductor thin film having a channel area and n-type or p-type impurity-doped source and drain areas. A gate electrode is formed in a position corresponding to the channel area. The TFT further includes gate insulating layer, which insulates the semiconductor thin film and the gate electrode. Source and drain electrodes are connected to each of the source and drain areas of the semiconductor thin film. In a TFT configured in this manner, a threshold voltage is modulated by changing a work function difference between the gate electrode and the semiconductor thin film.
摘要翻译：本发明涉及以简单的方式调制阈值电压的薄膜晶体管（TFT）。在一个实施例中，本发明的TFT还减少了处于断开状态的泄漏电流，并且确保了足够的阈值电压裕度，并且提供了具有该漏电流的平板显示器。 TFT包括具有沟道区和n型或p型杂质掺杂源极和漏极区的半导体薄膜。栅电极形成在与沟道区对应的位置。 TFT还包括使半导体薄膜和栅电极绝缘的栅极绝缘层。源极和漏极连接到半导体薄膜的源极和漏极区域中的每一个。在以这种方式配置的TFT中，通过改变栅电极和半导体薄膜之间的功函数差来调制阈值电压。

8. 发明授权

US07274343B2 Plasma display panel and apparatus and method for driving the same 失效
标题翻译：等离子显示面板及其驱动方法
公开(公告)号：US07274343B2
公开(公告)日：2007-09-25
申请号：US10445274
申请日：2003-05-23
申请人： Jun-Hyung Kim , Jin-Sung Kim , Myeong-Seob So , Nam-Sung Jung
发明人： Jun-Hyung Kim , Jin-Sung Kim , Myeong-Seob So , Nam-Sung Jung
IPC分类号： G09G3/10 , G09G3/28
CPC分类号： G09G3/2965 , G09G3/2932 , G09G2300/0408 , G09G2310/06 , G09G2330/024 , G09G2330/06
摘要： A PDP address driver circuit includes: an inductor coupled to a conductive pattern. A first current applier applyies a current of a first direction to the inductor and the conductive pattern while sustaining a panel capacitor at an address voltage. A discharger generates a resonance between the inductor and the panel capacitor to discharge the panel capacitor to 0V, while the current of the first direction flows to the inductor and the conductive pattern. A second current applier applyies a current of a second direction to the inductor and the conductive pattern while sustaining the panel capacitor at 0V. A charger generates a resonance between the inductor and the panel capacitor to charge the panel capacitor to the address voltage, while the current of the second direction flows to the inductor and the conductive pattern.
摘要翻译： PDP地址驱动器电路包括：耦合到导电图案的电感器。第一个当前的施加器将电流和第一方向施加到电感器和导电图案，同时在寻址电压下维持面板电容器。放电器在电感器和面板电容器之间产生谐振，以将面板电容器放电到0V，而第一方向的电流流向电感器和导电图案。第二个当前的施加器将电流和第二方向应用于电感器和导电图案，同时将面板电容器维持在0V。充电器在电感器和面板电容器之间产生谐振，以将面板电容器充电到寻址电压，而第二方向的电流流向电感器和导电图案。

9. 发明申请

US20060160280A1 Thin film transistor, a method for preparing the same and a flat panel display employing the same 有权
标题翻译：薄膜晶体管，其制备方法和采用该薄膜晶体管的平板显示器
公开(公告)号：US20060160280A1
公开(公告)日：2006-07-20
申请号：US11329865
申请日：2006-01-09
申请人： Min--Chul Suh , Myeong-Seob So , Jae-Bon Koo , Nam-Choul Yang
发明人： Min--Chul Suh , Myeong-Seob So , Jae-Bon Koo , Nam-Choul Yang
IPC分类号： H01L21/00 , H01L21/84 , H01L31/113
CPC分类号： H01L51/0545 , H01L51/0051 , H01L51/0052 , H01L51/0053 , H01L51/0062 , H01L51/0078 , H01L51/0541 , H01L51/0583
摘要： Provided are a thin film transistor, a method for preparing the same and a flat panel display employing the same. The thin film transistor includes a gate electrode, source and drain electrodes insulated from the gate electrode, a semiconductor layer insulated from the gate electrode and electrically connected to the source and drain electrodes, an insulating layer, and a carrier blocking layer interposed between the semiconductor layer and the insulating layer and preventing electrons or holes moving through semiconductor layer from being trapped in the insulating layer. Since the thin film transistor is constructed such that the carrier blocking layer is interposed between the semiconductor layer and the insulating layer, the electrons or holes injected into the semiconductor layer can be prevented from being trapped in the insulating layer, thereby suppressing hysteresis characteristic. In addition, a reliable flat panel display device can be manufactured using the thin film transistor.
摘要翻译：提供薄膜晶体管，其制备方法和采用该薄膜晶体管的平板显示器。薄膜晶体管包括栅电极，与栅电极绝缘的源电极和漏电极，与栅电极绝缘并电连接到源极和漏极的半导体层，绝缘层和插入在半导体之间的载流子阻挡层层和绝缘层，并且防止移动通过半导体层的电子或空穴被捕获在绝缘层中。由于薄膜晶体管被构造为使得载流子阻挡层插入在半导体层和绝缘层之间，因此可以防止注入到半导体层中的电子或空穴被捕获在绝缘层中，从而抑制滞后特性。此外，可以使用薄膜晶体管制造可靠的平板显示装置。

10. 发明授权

US07671359B2 Thin film transistor, a method for preparing the same and a flat panel display employing the same 有权
标题翻译：薄膜晶体管，其制备方法和采用该薄膜晶体管的平板显示器
公开(公告)号：US07671359B2
公开(公告)日：2010-03-02
申请号：US11329865
申请日：2006-01-09
申请人： Min-Chul Suh , Myeong-Seob So , Jae-Bon Koo , Nam-Choul Yang
发明人： Min-Chul Suh , Myeong-Seob So , Jae-Bon Koo , Nam-Choul Yang
IPC分类号： H01L51/00 , H01L51/40
CPC分类号： H01L51/0545 , H01L51/0051 , H01L51/0052 , H01L51/0053 , H01L51/0062 , H01L51/0078 , H01L51/0541 , H01L51/0583
摘要： Provided are a thin film transistor, a method for preparing the same and a flat panel display employing the same. The thin film transistor includes a gate electrode, source and drain electrodes insulated from the gate electrode, a semiconductor layer insulated from the gate electrode and electrically connected to the source and drain electrodes, an insulating layer, and a carrier blocking layer interposed between the semiconductor layer and the insulating layer and preventing electrons or holes moving through semiconductor layer from being trapped in the insulating layer. Since the thin film transistor is constructed such that the carrier blocking layer is interposed between the semiconductor layer and the insulating layer, the electrons or holes injected into the semiconductor layer can be prevented from being trapped in the insulating layer, thereby suppressing hysteresis characteristic. In addition, a reliable flat panel display device can be manufactured using the thin film transistor.
摘要翻译：提供薄膜晶体管，其制备方法和采用该薄膜晶体管的平板显示器。薄膜晶体管包括栅电极，与栅电极绝缘的源电极和漏电极，与栅电极绝缘并电连接到源极和漏极的半导体层，绝缘层和插入在半导体之间的载流子阻挡层层和绝缘层，并且防止移动通过半导体层的电子或空穴被捕获在绝缘层中。由于薄膜晶体管被构造为使得载流子阻挡层插入在半导体层和绝缘层之间，因此可以防止注入到半导体层中的电子或空穴被捕获在绝缘层中，从而抑制滞后特性。此外，可以使用薄膜晶体管制造可靠的平板显示装置。

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