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1. 发明授权

US08338815B2 Memory units and related semiconductor devices including nanowires 失效
标题翻译：存储器单元和包括纳米线的相关半导体器件
公开(公告)号：US08338815B2
公开(公告)日：2012-12-25
申请号：US12851268
申请日：2010-08-05
申请人： Moon-Sook Lee , Byeong-Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue
发明人： Moon-Sook Lee , Byeong-Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue
IPC分类号： H01L29/04 , H01L47/00
CPC分类号： H01L27/11507 , B82Y10/00 , H01L27/10 , H01L27/1021 , H01L27/24
摘要： Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes. Related memory units, methods of fabricating semiconductor devices and semiconductor devices are also provided.
摘要翻译：提供了一种制造存储器单元的方法，包括形成多个第一纳米线结构，每个第一纳米线结构包括在第一衬底上沿与第一衬底平行的第一方向延伸的第一纳米线和包围第一纳米线的第一电极层。第一电极层被部分地去除以在第一纳米线下方形成第一电极。填充第一基板上形成有第一纳米线和第一电极的结构之间的空间的第一绝缘层。在第一纳米线和第一绝缘层上形成第二电极层。多个第二纳米线形成在第二电极层上，每个第二纳米线沿垂直于第一方向的第二方向延伸。使用第二纳米线作为蚀刻掩模来部分蚀刻第二电极层以形成多个第二电极。还提供了相关的存储单元，制造半导体器件和半导体器件的方法。

2. 发明申请

US20090189152A1 FERROELECTRIC MEMORY DEVICE 审中-公开
标题翻译：电磁存储器件
公开(公告)号：US20090189152A1
公开(公告)日：2009-07-30
申请号：US12354990
申请日：2009-01-16
申请人： Byeong-Ok Cho , Moon-Sook Lee , Man-Hyoung Ryoo , Jung-Hyeon Kim , Takahiro Yasue
发明人： Byeong-Ok Cho , Moon-Sook Lee , Man-Hyoung Ryoo , Jung-Hyeon Kim , Takahiro Yasue
IPC分类号： H01L51/00 , H01L29/76
CPC分类号： H01L29/78391 , B82Y10/00 , G11C11/22 , H01L29/40111 , H01L29/516 , H01L29/6684
摘要： Provided is a ferroelectric memory device. The ferroelectric memory device includes an inorganic channel pattern on a substrate, a source electrode and a drain electrode spaced apart from each other on the substrate and contacting the inorganic channel pattern, a gate electrode disposed adjacent to the inorganic channel pattern, and an organic ferroelectric layer interposed between the inorganic channel pattern and the gate electrode.
摘要翻译：提供了一种铁电存储器件。铁电存储器件包括在衬底上的无机沟道图案，在衬底上彼此间隔开的源电极和漏电极，并与无机沟道图案接触，邻近无机沟道图案设置的栅电极和有机铁电体介于无机通道图案和栅电极之间的层。

3. 发明授权

US08105697B2 Polymer memory device and method of forming the same 有权
标题翻译：聚合物记忆装置及其形成方法
公开(公告)号：US08105697B2
公开(公告)日：2012-01-31
申请号：US11905510
申请日：2007-10-02
申请人： Byeong-Ok Cho , Takahiro Yasue , Moon-Sook Lee
发明人： Byeong-Ok Cho , Takahiro Yasue , Moon-Sook Lee
IPC分类号： B21D39/00 , B32B9/02
CPC分类号： H01L27/285 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L51/0035 , H01L51/0047 , Y10T428/12556 , Y10T428/31681 , Y10T428/31721
摘要： Provided is a polymer memory device and a method of forming the same. The polymer memory device may include a first electrode, a first curable polymer layer, a second electrode, a second curable polymer layer, and a third electrode. The first electrode may be disposed on a substrate. The first curable polymer layer may cover the first electrode. The second electrode may be disposed on the first curable polymer layer and cross over the first electrode. The second curable polymer layer may cover the second electrode. The third electrode may be disposed on the second curable polymer layer and cross over the second electrode. Each of the first curable polymer layer and the second curable polymer layer may contain a fullerene or a fullerene derivative.
摘要翻译：提供聚合物记忆装置及其形成方法。聚合物记忆装置可以包括第一电极，第一可固化聚合物层，第二电极，第二可固化聚合物层和第三电极。第一电极可以设置在基板上。第一可固化聚合物层可以覆盖第一电极。第二电极可以设置在第一可固化聚合物层上并与第一电极交叉。第二可固化聚合物层可以覆盖第二电极。第三电极可以设置在第二可固化聚合物层上并与第二电极交叉。第一可固化聚合物层和第二可固化聚合物层中的每一个可以含有富勒烯或富勒烯衍生物。

4. 发明申请

US20090085072A1 Biosensor using nanoscale material as transistor channel and method of fabricating the same 有权
标题翻译：使用纳米级材料作为晶体管沟道的生物传感器及其制造方法
公开(公告)号：US20090085072A1
公开(公告)日：2009-04-02
申请号：US12232243
申请日：2008-09-12
申请人： Moon-Sook Lee , Byeong-Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue , Jung-Hwan Hah
发明人： Moon-Sook Lee , Byeong-Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue , Jung-Hwan Hah
IPC分类号： H01L21/28 , H01L29/772
CPC分类号： G01N27/4145 , B82Y10/00 , B82Y15/00 , G01N27/4146 , H01L51/0595 , H01L2924/0002 , H01L2924/00
摘要： Example embodiments relate to a biosensor using a nanoscale material as a channel of a transistor and a method of fabricating the same. A biosensor according to example embodiments may include a plurality of insulating films. A first signal line and a second signal line may be interposed between the plurality of insulating films. A semiconductor nanostructure may be disposed on the plurality of insulating films, the semiconductor nanostructure having a first side electrically connected to the first signal line and a second side electrically connected to the second signal line. A plurality of probes may be coupled to the semiconductor nanostructure. A biosensor according to example embodiments may have a reduced analysis time.
摘要翻译：实施例涉及使用纳米级材料作为晶体管的沟道的生物传感器及其制造方法。根据示例性实施例的生物传感器可以包括多个绝缘膜。第一信号线和第二信号线可以插入在多个绝缘膜之间。半导体纳米结构可以设置在多个绝缘膜上，半导体纳米结构具有电连接到第一信号线的第一侧和与第二信号线电连接的第二侧。多个探针可以耦合到半导体纳米结构。根据示例性实施例的生物传感器可以具有减少的分析时间。

5. 发明申请

US20080131712A1 Polymer memory device and method of forming the same 有权
标题翻译：聚合物记忆装置及其形成方法
公开(公告)号：US20080131712A1
公开(公告)日：2008-06-05
申请号：US11905510
申请日：2007-10-02
申请人： Byeong-Ok Cho , Takahiro Yasue , Moon-Sook Lee
发明人： Byeong-Ok Cho , Takahiro Yasue , Moon-Sook Lee
IPC分类号： B32B27/06 , B05D5/12
CPC分类号： H01L27/285 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L51/0035 , H01L51/0047 , Y10T428/12556 , Y10T428/31681 , Y10T428/31721
摘要： Provided is a polymer memory device and a method of forming the same. The polymer memory device may include a first electrode, a first curable polymer layer, a second electrode, a second curable polymer layer, and a third electrode. The first electrode may be disposed on a substrate. The first curable polymer layer may cover the first electrode. The second electrode may be disposed on the first curable polymer layer and cross over the first electrode. The second curable polymer layer may cover the second electrode. The third electrode may be disposed on the second curable polymer layer and cross over the second electrode. Each of the first curable polymer layer and the second curable polymer layer may contain a fullerene or a fullerene derivative.
摘要翻译：提供聚合物记忆装置及其形成方法。聚合物记忆装置可以包括第一电极，第一可固化聚合物层，第二电极，第二可固化聚合物层和第三电极。第一电极可以设置在基板上。第一可固化聚合物层可以覆盖第一电极。第二电极可以设置在第一可固化聚合物层上并与第一电极交叉。第二可固化聚合物层可以覆盖第二电极。第三电极可以设置在第二可固化聚合物层上并与第二电极交叉。第一可固化聚合物层和第二可固化聚合物层中的每一个可以含有富勒烯或富勒烯衍生物。

6. 发明申请

US20100314600A1 Memory Units and Related Semiconductor Devices Including Nanowires 失效
标题翻译：包括纳米线的存储单元和相关半导体器件
公开(公告)号：US20100314600A1
公开(公告)日：2010-12-16
申请号：US12851268
申请日：2010-08-05
申请人： Moon-Sook Lee , Byeong-Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue
发明人： Moon-Sook Lee , Byeong-Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue
IPC分类号： H01L45/00
CPC分类号： H01L27/11507 , B82Y10/00 , H01L27/10 , H01L27/1021 , H01L27/24
摘要： Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes. Related memory units, methods of fabricating semiconductor devices and semiconductor devices are also provided.
摘要翻译：提供了一种制造存储器单元的方法，包括形成多个第一纳米线结构，每个第一纳米线结构包括在第一衬底上沿与第一衬底平行的第一方向延伸的第一纳米线和包围第一纳米线的第一电极层。第一电极层被部分地去除以在第一纳米线下方形成第一电极。填充第一基板上形成有第一纳米线和第一电极的结构之间的空间的第一绝缘层。在第一纳米线和第一绝缘层上形成第二电极层。多个第二纳米线形成在第二电极层上，每个第二纳米线沿垂直于第一方向的第二方向延伸。使用第二纳米线作为蚀刻掩模来部分蚀刻第二电极层以形成多个第二电极。还提供了相关的存储单元，制造半导体器件和半导体器件的方法。

7. 发明授权

US07790610B2 Methods of manufacturing memory units, and methods of manufacturing semiconductor devices 失效
标题翻译：制造存储器单元的方法以及制造半导体器件的方法
公开(公告)号：US07790610B2
公开(公告)日：2010-09-07
申请号：US12339577
申请日：2008-12-19
申请人： Moon-Sook Lee , Byeong-Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue
发明人： Moon-Sook Lee , Byeong-Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue
IPC分类号： H01L21/44
CPC分类号： H01L27/11507 , B82Y10/00 , H01L27/10 , H01L27/1021 , H01L27/24
摘要： Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes. Related memory units, methods of fabricating semiconductor devices and semiconductor devices are also provided.
摘要翻译：提供了一种制造存储器单元的方法，包括形成多个第一纳米线结构，每个第一纳米线结构包括在第一衬底上沿与第一衬底平行的第一方向延伸的第一纳米线和包围第一纳米线的第一电极层。第一电极层被部分地去除以在第一纳米线下方形成第一电极。填充第一基板上形成有第一纳米线和第一电极的结构之间的空间的第一绝缘层。在第一纳米线和第一绝缘层上形成第二电极层。多个第二纳米线形成在第二电极层上，每个第二纳米线沿垂直于第一方向的第二方向延伸。使用第二纳米线作为蚀刻掩模来部分蚀刻第二电极层以形成多个第二电极。还提供了相关的存储器单元，制造半导体器件和半导体器件的方法。

8. 发明授权

US07663141B2 Organic memory devices including organic material and fullerene layers 失效
标题翻译：有机记忆装置包括有机材料和富勒烯层
公开(公告)号：US07663141B2
公开(公告)日：2010-02-16
申请号：US11726888
申请日：2007-03-23
申请人： Byeong-Ok Cho , Moon-Sook Lee , Takahiro Yasue
发明人： Byeong-Ok Cho , Moon-Sook Lee , Takahiro Yasue
IPC分类号： H01L51/00
CPC分类号： H01L27/285 , B82Y10/00 , G11C11/5664 , G11C13/0014 , G11C13/0016 , G11C13/025 , G11C2211/5614 , G11C2213/72 , G11C2213/77 , H01L51/0026 , H01L51/0035 , H01L51/0036 , H01L51/0038 , H01L51/0039 , H01L51/0042 , H01L51/0046
摘要： An organic memory device may include a stack of an organic material layer and a fullerene layer to provide a data storage element between first and second electrodes. The data storage element may include an organic material layer formed on the first electrode, and a fullerene layer between the organic material layer and the second electrode. Methods of fabricating organic memory devices are also discussed.
摘要翻译：有机存储器件可以包括有机材料层和富勒烯层的叠层，以在第一和第二电极之间提供数据存储元件。数据存储元件可以包括形成在第一电极上的有机材料层和有机材料层和第二电极之间的富勒烯层。还讨论了制造有机存储器件的方法。

9. 发明申请

US20090209071A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20090209071A1
公开(公告)日：2009-08-20
申请号：US12388012
申请日：2009-02-18
申请人： Moon-Sook Lee , Byeong-Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue
发明人： Moon-Sook Lee , Byeong-Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue
IPC分类号： H01L21/8238
CPC分类号： H01L29/0665 , B82Y10/00 , G11C2213/16 , H01L21/02532 , H01L21/02546 , H01L21/02603 , H01L21/0262 , H01L21/02645 , H01L27/1052 , H01L27/24 , H01L29/0673 , H01L29/0676 , H01L29/775
摘要： First nanowires and second nanowires are alternately disposed and spaced apart on a first substrate in a second direction that is parallel to an adjacent major surface of the first substrate. Each of the first and second nanowires extends in a first direction that is perpendicular to the second direction, and the first and second nanowires are doped with first and second conductive types, respectively. A plurality of gate lines are formed that are at least partially disposed within the first substrate, that are spaced apart in a third direction, that extend in a fourth direction that is perpendicular to the third direction, and that partially enclose the first and second nanowires
摘要翻译：第一纳米线和第二纳米线在平行于第一基板的相邻主表面的第二方向上交替地设置和间隔在第一基板上。第一和第二纳米线中的每一个在垂直于第二方向的第一方向上延伸，并且第一和第二纳米线分别掺杂有第一和第二导电类型。形成多个栅极线，其至少部分地设置在第一基板内，在第三方向上间隔开，沿与第三方向垂直的第四方向延伸，并且部分地包围第一和第二纳米线

10. 发明申请

US20090162998A1 Methods of Manufacturing Memory Units, and Methods of Manufacturing Semiconductor Devices 失效
标题翻译：制造存储器单元的方法和制造半导体器件的方法
公开(公告)号：US20090162998A1
公开(公告)日：2009-06-25
申请号：US12339577
申请日：2008-12-19
申请人： Moon-Sook Lee , Byeong Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue
发明人： Moon-Sook Lee , Byeong Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue
IPC分类号： H01L21/768 , H01L21/20
CPC分类号： H01L27/11507 , B82Y10/00 , H01L27/10 , H01L27/1021 , H01L27/24
摘要： Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes. Related memory units, methods of fabricating semiconductor devices and semiconductor devices are also provided.
摘要翻译：提供了一种制造存储器单元的方法，包括形成多个第一纳米线结构，每个第一纳米线结构包括在第一衬底上沿与第一衬底平行的第一方向延伸的第一纳米线和包围第一纳米线的第一电极层。第一电极层被部分地去除以在第一纳米线下方形成第一电极。填充第一基板上形成有第一纳米线和第一电极的结构之间的空间的第一绝缘层。在第一纳米线和第一绝缘层上形成第二电极层。多个第二纳米线形成在第二电极层上，每个第二纳米线沿垂直于第一方向的第二方向延伸。使用第二纳米线作为蚀刻掩模来部分蚀刻第二电极层以形成多个第二电极。还提供了相关的存储单元，制造半导体器件和半导体器件的方法。

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