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1. 发明申请

US20050188129A1 Facilitating inter-DSP data communications 失效
标题翻译：促进DSP间数据通信
公开(公告)号：US20050188129A1
公开(公告)日：2005-08-25
申请号：US10783757
申请日：2004-02-20
申请人： Youseff Abdelilah , Bartholomew Blaner , Gordon Davis , Jeffrey Derby , Joseph Garvey , Malcolm Ware , Hua Ye
发明人： Youseff Abdelilah , Bartholomew Blaner , Gordon Davis , Jeffrey Derby , Joseph Garvey , Malcolm Ware , Hua Ye
IPC分类号： G06F3/00 , G06F13/28 , H04L29/06
CPC分类号： G06F13/28
摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.
摘要翻译：一种用于促进数字间数字信号处理（DSP）数据通信的方法，计算机程序产品和系统。直接存储器访问（DMA）控制器可以被配置为便于在耦合到DMA控制器的第一和第二DSP处理器核之间传输数据。 DMA控制器可以读取被称为“缓冲器描述符块”的数据结构来执行数据传送。缓冲器描述符块可以存储指示要检索和存储数据的源地址和目的地址。缓冲器描述符块还可以存储指示要传送的数据的大小的值，例如字节数。然后，DMA控制器可以将位于第一DSP处理器核心中的源地址处的数据以从缓冲器描述符块指示的大小（例如，字节数）传送到第二DSP处理器核心中的目的地地址。

2. 发明申请

US20080072005A1 Facilitating Inter-DSP Data Communications 失效
标题翻译：促进DSP间数据通信
公开(公告)号：US20080072005A1
公开(公告)日：2008-03-20
申请号：US11944028
申请日：2007-11-21
申请人： Youseff Abdelilah , Bartholomew Blaner , Gordon Davis , Jeffrey Derby , Joseph Garvey , Malcolm Ware , Hua Ye
发明人： Youseff Abdelilah , Bartholomew Blaner , Gordon Davis , Jeffrey Derby , Joseph Garvey , Malcolm Ware , Hua Ye
IPC分类号： G06F12/02
CPC分类号： G06F13/28
摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.
摘要翻译：一种用于促进数字间数字信号处理（DSP）数据通信的方法，计算机程序产品和系统。直接存储器访问（DMA）控制器可以被配置为便于在耦合到DMA控制器的第一和第二DSP处理器核之间传输数据。 DMA控制器可以读取被称为“缓冲器描述符块”的数据结构来执行数据传送。缓冲器描述符块可以存储指示要检索和存储数据的源地址和目的地址。缓冲器描述符块还可以存储指示要传送的数据的大小的值，例如字节数。然后，DMA控制器可以将位于第一DSP处理器核心中的源地址处的数据以从缓冲器描述符块指示的大小（例如，字节数）传送到第二DSP处理器核心中的目的地地址。

3. 发明申请

US20080010390A1 Facilitating Inter-DSP Data Communications 审中-公开
公开(公告)号：US20080010390A1
公开(公告)日：2008-01-10
申请号：US11856509
申请日：2007-09-17
申请人： Youseff Abdelilah , Bartholomew Blaner , Gordon Davis , Jeffrey Derby , Joseph Garvey , Malcolm Ware , Hua Ye
发明人： Youseff Abdelilah , Bartholomew Blaner , Gordon Davis , Jeffrey Derby , Joseph Garvey , Malcolm Ware , Hua Ye
IPC分类号： G06F3/00
CPC分类号： G06F13/28
摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.

4. 发明申请

US20060209898A1 Network congestion detection and automatic fallback: methods, systems & program products 失效
标题翻译：网络拥塞检测和自动回退：方法，系统和程序产品
公开(公告)号：US20060209898A1
公开(公告)日：2006-09-21
申请号：US11348417
申请日：2006-02-07
申请人： Youssef Abdelilah , Gordon Davis , Jeffrey Derby , Dongming Hwang , Clark Jeffries , Malcolm Ware , Hua Ye
发明人： Youssef Abdelilah , Gordon Davis , Jeffrey Derby , Dongming Hwang , Clark Jeffries , Malcolm Ware , Hua Ye
IPC分类号： H04J3/18
CPC分类号： H04L47/10 , H04L12/6418 , H04L29/06027 , H04L47/12 , H04L47/2425 , H04L47/263 , H04L47/70 , H04L47/745 , H04L47/748 , H04L47/762 , H04L65/1009 , H04L65/607 , H04L65/80 , H04L2012/6481 , H04L2012/6497
摘要： A codec detects congestion in a packet network and responds via a session control protocol to re-negotiate codec-type and/or parameters with the receiving codec to reduce bit rate for supporting a session. Once the connection and session are established, encoded packets start flowing between the two codecs. A control entity sends and receives network congestion control packets periodically in the session. The congestion control packets provide a “heartbeat” signal to the receiving codec. When the network is not congested, all “heartbeat” packets will be passed through the network. As network congestion increases, routers within the network discard excess packets to prevent network failure. The codecs respond to the missing packets by slowing down the bit rate or proceeding to renegotiate a lower bit rate via the session control protocol. If there are no missing packets, the codecs detect if the session is operating at the highest bit rate, and if not, re-negotiate a higher bit rate.
摘要翻译：编解码器检测分组网络中的拥塞，并通过会话控制协议进行响应，以使用接收编解码器重新协商编解码器类型和/或参数，以减少支持会话的比特率。一旦建立了连接和会话，编码的数据包将在两个编解码器之间开始流动。控制实体在会话中定期发送和接收网络拥塞控制报文。拥塞控制分组向接收编解码器提供“心跳”信号。当网络不拥塞时，所有“心跳”数据包将通过网络传递。随着网络拥塞的增加，网络内的路由器丢弃多余的数据包，防止网络故障。编解码器通过减慢比特率或通过会话控制协议进行重新协商较低的比特率来响应丢失的分组。如果没有丢失数据包，则编解码器检测会话是否以最高比特率运行，如果不是，则重新协商更高的比特率。

5. 发明申请

US20060039457A1 System and method for controlling line driver power in digital subscriber line modems 有权
公开(公告)号：US20060039457A1
公开(公告)日：2006-02-23
申请号：US11237001
申请日：2005-09-28
申请人： Gordon Davis , Jeffrey Derby , Evangelos Eleftheriou , Sedat Oelcer , Malcolm Ware
发明人： Gordon Davis , Jeffrey Derby , Evangelos Eleftheriou , Sedat Oelcer , Malcolm Ware
IPC分类号： H04B1/38
CPC分类号： H04L25/028 , H04L27/2626 , H04M11/062 , Y02D50/44
摘要： A low power DSL modem transmitter, suitable for incorporation in integrated DSLAM server line cards, transmits full power physical frames which include a control channel and a data field when data is available for transmission and physical frames having only a control channel or a control channel and a low power synchronization field when data is not available for transmission. And a method for controlling the total power dissipated in the integrated DSLAM by selectively restricting the flow of data packets to the DSLs.

6. 发明申请

US20060265576A1 Methods and apparatus for dynamically switching processor mode 有权
标题翻译：用于动态切换处理器模式的方法和装置
公开(公告)号：US20060265576A1
公开(公告)日：2006-11-23
申请号：US11132658
申请日：2005-05-19
申请人： Gordon Davis , Jeffrey Derby
发明人： Gordon Davis , Jeffrey Derby
IPC分类号： G06F9/44
CPC分类号： G06F9/3017
摘要： In a first aspect, a first processing method is provided. The first processing method includes the steps of (1) operating a processor in a first mode based on an operand size associated with a first instruction received by the processor; and (2) dynamically switching the processor operation mode from the first mode to a second mode based on a different operand size associated with a second instruction received by the processor. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一处理方法。第一处理方法包括以下步骤：（1）基于与由处理器接收的第一指令相关联的操作数大小，以第一模式操作处理器; 和（2）基于与由处理器接收的第二指令相关联的不同操作数大小，将处理器操作模式从第一模式动态地切换到第二模式。提供了许多其他方面。

7. 发明申请

US20060265555A1 Methods and apparatus for sharing processor resources 审中-公开
标题翻译：用于共享处理器资源的方法和设备
公开(公告)号：US20060265555A1
公开(公告)日：2006-11-23
申请号：US11132656
申请日：2005-05-19
申请人： Gordon Davis , Jeffrey Derby
发明人： Gordon Davis , Jeffrey Derby
IPC分类号： G06F13/28
CPC分类号： G06F9/3851 , G06F9/30112 , G06F9/3012 , G06F9/384
摘要： In a first aspect, a first method is provided for sharing processor resources. The first method includes the steps of (1) grouping a plurality of physical registers into at least one array, wherein registers in each of the at least one array share read and write ports and wherein at least two types of execution units are coupled to each of the at least one array; and (2) storing different types of data at different times in at least one of the registers from the at least one array, wherein each of the different types of data is associated with at least a different one of the execution units. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种用于共享处理器资源的第一种方法。第一种方法包括以下步骤：（1）将多个物理寄存器分组成至少一个阵列，其中至少一个阵列中的每一个中的寄存器共享读取和写入端口，并且其中至少两种类型的执行单元耦合到每个的所述至少一个阵列; 以及（2）在来自所述至少一个阵列的至少一个寄存器中的不同时间存储不同类型的数据，其中所述不同类型的数据中的每一个与至少一个所述执行单元相关联。提供了许多其他方面。

8. 发明申请

US20060265552A1 Prefetch mechanism based on page table attributes 有权
标题翻译：基于页表属性的预取机制
公开(公告)号：US20060265552A1
公开(公告)日：2006-11-23
申请号：US11131582
申请日：2005-05-18
申请人： Gordon Davis , Thomas Genduso , Harold Kossman , Robert Todd
发明人： Gordon Davis , Thomas Genduso , Harold Kossman , Robert Todd
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F12/10 , G06F12/1027 , G06F2212/6024 , G06F2212/6026
摘要： A prefetch mechanism using prefetch attributes is disclosed. In one aspect, an explicit request for data stored in a memory is provided, and a prefetch attribute in a page table entry associated with the explicit request is examined to determine whether to provide one or more prefetch requests based on the prefetch attribute. Another aspect includes determining dynamic prefetch attributes for use in prefetching data, in which prefetch attributes are adjusted based on memory access requests that target next sequential blocks of memory relative to the most recent previous access in a page of memory.
摘要翻译：公开了一种使用预取属性的预取机制。在一个方面，提供对存储在存储器中的数据的显式请求，并且检查与显式请求相关联的页表条目中的预取属性，以基于预取属性来确定是否提供一个或多个预取请求。另一方面包括确定用于在预取数据中使用的动态预取属性，其中基于存储器访问请求来调整预取属性，所述存储器访问请求相对于存储器页面中最近的先前存取的下一个顺序存储块。

9. 发明申请

US20060271576A1 METHOD AND STRUCTURE FOR DELETING LEAVES IN TREE TABLE STRUCTURES 失效
标题翻译：树木结构中的叶片去除方法与结构
公开(公告)号：US20060271576A1
公开(公告)日：2006-11-30
申请号：US11462404
申请日：2006-08-04
申请人： Claude Basso , Jean Calvignac , Gordon Davis , Marco Heddes , Piyush Patel , Steven Perrin , Grayson Randall , Sonia Rovner
发明人： Claude Basso , Jean Calvignac , Gordon Davis , Marco Heddes , Piyush Patel , Steven Perrin , Grayson Randall , Sonia Rovner
IPC分类号： G06F7/00
CPC分类号： G06F17/30625 , Y10S707/99936 , Y10S707/99942 , Y10S707/99943
摘要： A technique is provided to delete a leaf from a Patricia tree having a direct table and a plurality of PSCB's which decode portions of the pattern of a leaf in the tree without shutting down the functioning of the tree. A leaf having a pattern is identified as a leaf to be deleted. Using the pattern, the tree is walked to identify the location of the leaf to be deleted. The leaf to be deleted is identified and deleted, and any relevant PSCB modified, if necessary. The technique also is applicable to deleting a prefix of a prefix.
摘要翻译：提供一种技术来从具有直接表的帕特里夏树和多个PSCB中删除叶，该PSCB解码树中的叶的图案的部分，而不关闭树的功能。具有图案的叶被识别为要被删除的叶。使用图案，树被移动以识别要删除的叶子的位置。要删除的叶被识别和删除，并且必要时修改任何相关的PSCB。该技术也适用于删除前缀的前缀。

10. 发明申请

US20060168583A1 Systems and methods for TDM multithreading 失效
标题翻译： TDM多线程的系统和方法
公开(公告)号：US20060168583A1
公开(公告)日：2006-07-27
申请号：US11042692
申请日：2005-01-25
申请人： Claude Basso , Jean Calvignac , Chih-jen Chang , Gordon Davis , Harm Hofstee , Fabrice Verplanken , Colin Verrilli
发明人： Claude Basso , Jean Calvignac , Chih-jen Chang , Gordon Davis , Harm Hofstee , Fabrice Verplanken , Colin Verrilli
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/4843
摘要： Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.
摘要翻译：公开了用于在多线程数字处理器的流水线中分发线程指令的系统和方法。更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。如果要选择的线程无法执行，则选择补充线程执行。

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