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1. 发明申请

US20140036909A1 SINGLE INSTRUCTION PROCESSING OF NETWORK PACKETS 审中-公开
标题翻译：网络包的单指令处理
公开(公告)号：US20140036909A1
公开(公告)日：2014-02-06
申请号：US13926085
申请日：2013-06-25
申请人： Bryan E. Veal , Travis T. Schluessler
发明人： Bryan E. Veal , Travis T. Schluessler
IPC分类号： H04L12/947
CPC分类号： H04L49/25 , G06F9/3885 , G06F9/3887 , H04L49/9094
摘要： Executing a single instruction/multiple data (SIMD) instruction of a program to process a vector of data wherein each element of the packet vector corresponds to a different received packet.
摘要翻译：执行程序的单指令/多数据（SIMD）指令以处理数据向量，其中分组向量的每个元素对应于不同的接收分组。

2. 发明授权

US09317892B2 Method and device to augment volatile memory in a graphics subsystem with non-volatile memory 有权
标题翻译：在具有非易失性存储器的图形子系统中增加易失性存储器的方法和装置
公开(公告)号：US09317892B2
公开(公告)日：2016-04-19
申请号：US13977261
申请日：2011-12-28
申请人： Bryan E. Veal , Travis T. Schluessler , Murali Ramadoss , Balaji Vembu
发明人： Bryan E. Veal , Travis T. Schluessler , Murali Ramadoss , Balaji Vembu
IPC分类号： G09G5/39 , G06T1/60 , G11C16/34
CPC分类号： G06T1/60 , G11C16/349
摘要： Methods and devices to augment volatile memory in a graphics subsystem with certain types of non-volatile memory are described. In one embodiment, includes storing one or more static or near-static graphics resources in a non-volatile random access memory (NVRAM). The NVRAM is directly accessible by a graphics processor using at least memory store and load commands. The method also includes a graphics processor executing a graphics application. The graphics processor sends a request using a memory load command for an address corresponding to at least one static or near-static graphics resources stored in the NVRAM. The method also includes directly loading the requested graphics resource from the NVRAM into a cache for the graphics processor in response to the memory load command.
摘要翻译：描述了在具有某些类型的非易失性存储器的图形子系统中增加易失性存储器的方法和装置。在一个实施例中，包括将一个或多个静态或近静态图形资源存储在非易失性随机存取存储器（NVRAM）中。 NVRAM可直接由图形处理器使用，至少使用内存存储和加载命令。该方法还包括执行图形应用的图形处理器。图形处理器使用存储器加载命令来发送对应于存储在NVRAM中的至少一个静态或近静态图形资源的地址的请求。该方法还包括响应于存储器加载命令将所请求的图形资源从NVRAM直接加载到图形处理器的高速缓存中。

3. 发明授权

US08493979B2 Single instruction processing of network packets 有权
公开(公告)号：US08493979B2
公开(公告)日：2013-07-23
申请号：US12317844
申请日：2008-12-30
申请人： Bryan E. Veal , Travis T. Schluessler
发明人： Bryan E. Veal , Travis T. Schluessler
IPC分类号： H04L12/28
CPC分类号： H04L49/25 , G06F9/3885 , G06F9/3887 , H04L49/9094
摘要： Executing a single instruction/multiple data (SIMD) instruction of a program to process a vector of data wherein each element of the packet vector corresponds to a different received packet.

4. 发明申请

US20100165991A1 SIMD processing of network packets 有权
标题翻译： SIMD处理网络数据包
公开(公告)号：US20100165991A1
公开(公告)日：2010-07-01
申请号：US12317844
申请日：2008-12-30
申请人： Bryan E. Veal , Travis T. Schluessler
发明人： Bryan E. Veal , Travis T. Schluessler
IPC分类号： H04L12/56
CPC分类号： H04L49/25 , G06F9/3885 , G06F9/3887 , H04L49/9094
摘要： Executing a single instruction/multiple data (SIMD) instruction of a program to process a vector of data wherein each element of the packet vector corresponds to a different received packet.
摘要翻译：执行程序的单指令/多数据（SIMD）指令以处理数据向量，其中分组向量的每个元素对应于不同的接收分组。

5. 发明授权

US08984309B2 Reducing network latency during low power operation 有权
标题翻译：在低功耗运行期间减少网络延迟
公开(公告)号：US08984309B2
公开(公告)日：2015-03-17
申请号：US12313548
申请日：2008-11-21
申请人： Mazhar I. Memon , Steen K. Larsen , Bryan E. Veal , Daniel S. Lake , Travis T. Schluessler
发明人： Mazhar I. Memon , Steen K. Larsen , Bryan E. Veal , Daniel S. Lake , Travis T. Schluessler
IPC分类号： G06F1/00 , H04L12/861 , G06F1/32 , H04L12/12
CPC分类号： H04L47/12 , G06F1/3209 , H04L12/12 , H04L49/90 , Y02B70/32 , Y02D50/40
摘要： In one embodiment, the present invention includes a method for receiving an incoming packet in a packet buffer and associating it with a flow identifier. Based on the flow identifier, a core to which the incoming packet is to be directed may be determined, and a power management hint can be transmitted to cause the core to be powered up. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在分组缓冲器中接收输入分组并将其与流标识符相关联的方法。基于流标识符，可以确定输入分组将被引导到的核心，并且可以发送功率管理提示以使得核心被加电。描述和要求保护其他实施例。

6. 发明申请

US20140198116A1 A METHOD AND DEVICE TO AUGMENT VOLATILE MEMORY IN A GRAPHICS SUBSYSTEM WITH NON-VOLATILE MEMORY 有权
标题翻译：具有非易失性存储器的图形子系统中的波动记忆体的方法和装置
公开(公告)号：US20140198116A1
公开(公告)日：2014-07-17
申请号：US13977261
申请日：2011-12-28
申请人： Bryan E. Veal , Travis T. Schluessler , Murali Ramadoss , Balaji Vembu
发明人： Bryan E. Veal , Travis T. Schluessler , Murali Ramadoss , Balaji Vembu
IPC分类号： G06T1/60
CPC分类号： G06T1/60 , G11C16/349
摘要： Methods and devices to augment volatile memory in a graphics subsystem with certain types of non-volatile memory are described. In one embodiment, includes storing one or more static or near-static graphics resources in a non-volatile random access memory (NVRAM). The NVRAM is directly accessible by a graphics processor using at least memory store and load commands. The method also includes a graphics processor executing a graphics application. The graphics processor sends a request using a memory load command for an address corresponding to at least one static or near-static graphics resources stored in the NVRAM. The method also includes directly loading the requested graphics resource from the NVRAM into a cache for the graphics processor in response to the memory load command.
摘要翻译：描述了在具有某些类型的非易失性存储器的图形子系统中增加易失性存储器的方法和装置。在一个实施例中，包括将一个或多个静态或近静态图形资源存储在非易失性随机存取存储器（NVRAM）中。 NVRAM可直接由图形处理器使用，至少使用内存存储和加载命令。该方法还包括执行图形应用的图形处理器。图形处理器使用存储器加载命令来发送对应于存储在NVRAM中的至少一个静态或近静态图形资源的地址的请求。该方法还包括响应于存储器加载命令将所请求的图形资源从NVRAM直接加载到图形处理器的高速缓存中。

7. 发明申请

US20100131781A1 Reducing network latency during low power operation 有权
标题翻译：在低功耗运行期间减少网络延迟
公开(公告)号：US20100131781A1
公开(公告)日：2010-05-27
申请号：US12313548
申请日：2008-11-21
申请人： Mazhar I. Memon , Steen K. Larsen , Bryan E. Veal , Daniel S. Lake , Travis T. Schluessler
发明人： Mazhar I. Memon , Steen K. Larsen , Bryan E. Veal , Daniel S. Lake , Travis T. Schluessler
IPC分类号： G06F1/26 , G06F15/00
CPC分类号： H04L47/12 , G06F1/3209 , H04L12/12 , H04L49/90 , Y02B70/32 , Y02D50/40
摘要： In one embodiment, the present invention includes a method for receiving an incoming packet in a packet buffer and associating it with a flow identifier. Based on the flow identifier, a core to which the incoming packet is to be directed may be determined, and a power management hint can be transmitted to cause the core to be powered up. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在分组缓冲器中接收输入分组并将其与流标识符相关联的方法。基于流标识符，可以确定输入分组将被引导到的核心，并且可以发送功率管理提示以使得核心被加电。描述和要求保护其他实施例。

8. 发明申请

US20110153893A1 Source Core Interrupt Steering 有权
标题翻译：源核心中断转向
公开(公告)号：US20110153893A1
公开(公告)日：2011-06-23
申请号：US12641604
申请日：2009-12-18
申请人： Annie Foong , Bryan E. Veal
发明人： Annie Foong , Bryan E. Veal
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F9/4812
摘要： An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein.
摘要翻译：本发明的实施例包括（i）接收与处理器源核心对应的核心标识符; （ii）从所述源核心接收与所述核心标识符相关联的输入/输出请求; （iii）并且基于核心标识符将对应于请求的中断引导到源核心。本文描述了其它实施例。

9. 发明申请

US20150278208A1 HASH MAP SUPPORT IN A STORAGE DEVICE 有权
标题翻译：存储设备中的HASH地图支持
公开(公告)号：US20150278208A1
公开(公告)日：2015-10-01
申请号：US14228822
申请日：2014-03-28
申请人： Annie Foong , Bryan E. Veal
发明人： Annie Foong , Bryan E. Veal
IPC分类号： G06F17/30
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0631 , G06F3/0638 , G06F3/064 , G06F3/0652 , G06F3/0679 , G06F3/0688
摘要： In an embodiment, a storage device may include device processing logic. The device processing logic may acquire a command associated with a key-value pair (KVP). The command may be, for example, a get, set, or delete command. The KVP may include a hash value and an item. The hash value may be a key in the KVP and the item may be a value in the KVP. The device processing logic may translate the acquired command into one or more block-oriented commands which may be executed by the device processing logic to perform various operations on the storage device.
摘要翻译：在一个实施例中，存储设备可以包括设备处理逻辑。设备处理逻辑可以获取与键值对（KVP）相关联的命令。该命令可以是例如get，set或delete命令。 KVP可以包括散列值和项目。散列值可以是KVP中的密钥，并且该项可以是KVP中的值。设备处理逻辑可以将所获取的命令转换成一个或多个面向块的命令，该命令可由设备处理逻辑执行以在存储设备上执行各种操作。

10. 发明申请

US20140089728A1 METHOD AND APPARATUS FOR SYNCHRONIZING STORAGE VOLUMES 有权
标题翻译：用于同步存储体积的方法和装置
公开(公告)号：US20140089728A1
公开(公告)日：2014-03-27
申请号：US13628257
申请日：2012-09-27
申请人： Bryan E. Veal , Annie Foong
发明人： Bryan E. Veal , Annie Foong
IPC分类号： G06F11/20
CPC分类号： G06F11/1474
摘要： A disk array redundancy controller ensures integrity of a mirrored or RAID storage array supporting a host system and minimizes recovery time responsive to a storage volume failure by traversing caches of recently written blocks to identify partially flushed stripes of data and recovering the inconsistent stripes on each of the storage volumes based on a master copy derived from the scan of all pre-failure caches of the storage array. The storage array employs nonvolatile caches in conjunction with solid state drive (SSD) storage volumes, allowing post-failure recovery of recently written blocks. A cache depth at least sufficient to store the largest stripe, or set of blocks, from the host ensures recovery of the entire stripe from a collective scan of the caches of all storage volumes of the storage array.
摘要翻译：磁盘阵列冗余控制器确保支持主机系统的镜像或RAID存储阵列的完整性，并通过遍历最近写入的块的高速缓存来最小化响应于存储卷故障的恢复时间，以识别部分刷新的数据条带，并恢复每个存储卷基于从扫描存储阵列的所有故障前高速缓存得到的主副本。存储阵列采用与固态驱动器（SSD）存储卷结合的非易失性高速缓存，允许最近写入的块的故障后恢复。至少足以存储来自主机的最大条带或一组块的高速缓存深度确保从存储阵列的所有存储卷的高速缓存的集合扫描中恢复整个条带。

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