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    • 2. 发明申请
    • METHOD AND APPARATUS FOR SYNCHRONIZING STORAGE VOLUMES
    • 用于同步存储体积的方法和装置
    • US20140089728A1
    • 2014-03-27
    • US13628257
    • 2012-09-27
    • Bryan E. VealAnnie Foong
    • Bryan E. VealAnnie Foong
    • G06F11/20
    • G06F11/1474
    • A disk array redundancy controller ensures integrity of a mirrored or RAID storage array supporting a host system and minimizes recovery time responsive to a storage volume failure by traversing caches of recently written blocks to identify partially flushed stripes of data and recovering the inconsistent stripes on each of the storage volumes based on a master copy derived from the scan of all pre-failure caches of the storage array. The storage array employs nonvolatile caches in conjunction with solid state drive (SSD) storage volumes, allowing post-failure recovery of recently written blocks. A cache depth at least sufficient to store the largest stripe, or set of blocks, from the host ensures recovery of the entire stripe from a collective scan of the caches of all storage volumes of the storage array.
    • 磁盘阵列冗余控制器确保支持主机系统的镜像或RAID存储阵列的完整性,并通过遍历最近写入的块的高速缓存来最小化响应于存储卷故障的恢复时间,以识别部分刷新的数据条带,并恢复每个 存储卷基于从扫描存储阵列的所有故障前高速缓存得到的主副本。 存储阵列采用与固态驱动器(SSD)存储卷结合的非易失性高速缓存,允许最近写入的块的故障后恢复。 至少足以存储来自主机的最大条带或一组块的高速缓存深度确保从存储阵列的所有存储卷的高速缓存的集合扫描中恢复整个条带。
    • 3. 发明申请
    • COMMUNICATION BETWEEN PROCESSOR CORE PARTITIONS
    • 处理器核心部分之间的通信
    • US20090319705A1
    • 2009-12-24
    • US12141725
    • 2008-06-18
    • Annie FoongBryan E. VealArun Raghunath
    • Annie FoongBryan E. VealArun Raghunath
    • G06F13/00
    • G06F15/16
    • In an embodiment, a method is provided that may include providing a first address space exclusively and coherently accessible by a first processor core partition in a platform. A second address space may be provided in this embodiment that is exclusively and coherently accessible by a second processor core partition in the platform. Also in this embodiment, a third address space in the platform may be provided that is accessible, at least in part, by both the first and second processor core partitions and may be to permit communication between the first and second processor core partitions of at least one packet and at least one descriptor associated with the at least one packet. The at least one descriptor may indicate, at least in part, one or more locations in the third address space to store, at least in part, the at least one packet. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.
    • 在一个实施例中,提供了一种方法,其可以包括提供由平台中的第一处理器核心分区独占且可相干访问的第一地址空间。 可以在该实施例中提供第二地址空间,其由平台中的第二处理器核心分区专门地和相干地访问。 同样在该实施例中,可以提供平台中的第三地址空间,其至少部分地由第一和第二处理器核分区可访问,并且可以允许至少在第一和第二处理器核分区之间进行通信 一个分组和与所述至少一个分组相关联的至少一个描述符。 至少一个描述符可以至少部分地指示第三地址空间中的一个或多个位置,以至少部分地存储至少一个分组。 当然,在不脱离本实施例的情况下,许多替代,修改和变化是可能的。
    • 7. 发明授权
    • Communication between processor core partitions with exclusive read or write to descriptor queues for shared memory space
    • 处理器核心分区之间的通信,具有独占读或写到共享存储空间的描述符队列
    • US07650488B2
    • 2010-01-19
    • US12141725
    • 2008-06-18
    • Annie FoongBryan E. VealArun Raghunath
    • Annie FoongBryan E. VealArun Raghunath
    • G06F15/167
    • G06F15/16
    • In an embodiment, a method is provided that may include providing a first address space exclusively and coherently accessible by a first processor core partition in a platform. A second address space may be provided in this embodiment that is exclusively and coherently accessible by a second processor core partition in the platform. Also in this embodiment, a third address space in the platform may be provided that is accessible, at least in part, by both the first and second processor core partitions and may be to permit communication between the first and second processor core partitions of at least one packet and at least one descriptor associated with the at least one packet. The at least one descriptor may indicate, at least in part, one or more locations in the third address space to store, at least in part, the at least one packet. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.
    • 在一个实施例中,提供了一种方法,其可以包括提供由平台中的第一处理器核心分区独占且可相干访问的第一地址空间。 可以在该实施例中提供第二地址空间,其由平台中的第二处理器核心分区专门地和相干地访问。 同样在该实施例中,可以提供平台中的第三地址空间,其至少部分地由第一和第二处理器核分区可访问,并且可以允许至少在第一和第二处理器核分区之间进行通信 一个分组和与所述至少一个分组相关联的至少一个描述符。 至少一个描述符可以至少部分地指示第三地址空间中的一个或多个位置,以至少部分地存储至少一个分组。 当然,在不脱离本实施例的情况下,许多替代,修改和变化是可能的。