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1. 发明授权

US09003160B2 Active buffered memory 有权
标题翻译：主动缓冲内存
公开(公告)号：US09003160B2
公开(公告)日：2015-04-07
申请号：US13566019
申请日：2012-08-03
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , James A. Kahle , Jaime H. Moreno , Ravi Nair
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , James A. Kahle , Jaime H. Moreno , Ravi Nair
IPC分类号： G06F12/10 , G06F9/445
CPC分类号： G06F9/44578 , G06F12/10 , Y02D10/13
摘要： According to one embodiment of the present invention, a method for operating a memory device that includes memory and a processing element includes receiving, in the processing element, a command from a requestor, loading, in the processing element, a program based on the command, the program comprising a load instruction loaded from a first memory location in the memory, and performing, by the processing element, the program, the performing including loading data in the processing element from a second memory location in the memory. The method also includes generating, by the processing element, a virtual address of the second memory location based on the load instruction and translating, by the processing element, the virtual address into a real address.
摘要翻译：根据本发明的一个实施例，一种用于操作包括存储器和处理元件的存储器件的方法包括在处理元件中接收来自请求器的命令，在处理元件中接收基于该命令的程序所述程序包括从所述存储器中的第一存储器位置加载的加载指令，并且由所述处理元件执行所述程序，所述执行包括来自所述存储器中的第二存储器位置的所述处理元件中的加载数据。该方法还包括由处理元件基于加载指令产生第二存储器位置的虚拟地址，并由处理元件将虚拟地址转换为实际地址。

2. 发明申请

US20140040592A1 ACTIVE BUFFERED MEMORY 有权
标题翻译：主动缓冲存储器
公开(公告)号：US20140040592A1
公开(公告)日：2014-02-06
申请号：US13566019
申请日：2012-08-03
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , James A. Kahle , Jaime H. Moreno , Ravi Nair
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , James A. Kahle , Jaime H. Moreno , Ravi Nair
IPC分类号： G06F12/10
CPC分类号： G06F9/44578 , G06F12/10 , Y02D10/13
摘要： According to one embodiment of the present invention, a method for operating a memory device that includes memory and a processing element includes receiving, in the processing element, a command from a requestor, loading, in the processing element, a program based on the command, the program comprising a load instruction loaded from a first memory location in the memory, and performing, by the processing element, the program, the performing including loading data in the processing element from a second memory location in the memory. The method also includes generating, by the processing element, a virtual address of the second memory location based on the load instruction and translating, by the processing element, the virtual address into a real address.
摘要翻译：根据本发明的一个实施例，一种用于操作包括存储器和处理元件的存储器件的方法包括在处理元件中接收来自请求器的命令，在处理元件中接收基于该命令的程序所述程序包括从所述存储器中的第一存储器位置加载的加载指令，并且由所述处理元件执行所述程序，所述执行包括来自所述存储器中的第二存储器位置的所述处理元件中的加载数据。该方法还包括由处理元件基于加载指令产生第二存储器位置的虚拟地址，并由处理元件将虚拟地址转换为实际地址。

3. 发明申请

US20140040599A1 PACKED LOAD/STORE WITH GATHER/SCATTER 审中-公开
标题翻译：包装加载/存储与GATHER / SCATTER
公开(公告)号：US20140040599A1
公开(公告)日：2014-02-06
申请号：US13569363
申请日：2012-08-08
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/30043 , G06F9/30036
摘要： Embodiments relate to packed loading and storing of data. An aspect includes a system for packed loading and storing of distributed data. The system includes memory and a processing element configured to communicate with the memory. The processing element is configured to perform a method including fetching and decoding an instruction for execution by the processing element. A plurality of individually addressable data elements is gathered from non-contiguous locations in the memory which are narrower than a nominal width of register file elements in the processing element based on the instruction. The processing element packs and loads the data elements into register file elements of a register file entry based on the instruction, such that at least two of the data elements gathered from the non-contiguous locations in the memory are packed and loaded into a single register file element of the register file entry.
摘要翻译：实施例涉及数据的打包加载和存储。一个方面包括用于打包加载和存储分布式数据的系统。该系统包括存储器和被配置为与存储器通信的处理元件。处理元件被配置为执行一种方法，包括对由处理元件执行的指令进行取出和解码。基于该指令，多个可单独寻址的数据元素从存储器中的不连续位置收集，该位置比处理元件中的寄存器文件元素的标称宽度窄。处理元件基于指令将数据元素打包并加载到寄存器文件条目的寄存器文件元素中，使得从存储器中的非连续位置收集的至少两个数据元素被打包并加载到单个寄存器注册文件条目的文件元素。

4. 发明申请

US20140040596A1 PACKED LOAD/STORE WITH GATHER/SCATTER 有权
标题翻译：包装加载/存储与GATHER / SCATTER
公开(公告)号：US20140040596A1
公开(公告)日：2014-02-06
申请号：US13566141
申请日：2012-08-03
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/30043 , G06F9/30036
摘要： Embodiments relate to packed loading and storing of data. An aspect includes a method for packed loading and storing of data distributed in a system that includes memory and a processing element. The method includes fetching and decoding an instruction for execution by the processing element. The processing element gathers a plurality of individually addressable data elements from non-contiguous locations in the memory which are narrower than a nominal width of register file elements in the processing element based on the instruction. The data elements are packed and loaded into register file elements of a register file entry by the processing element based on the instruction, such that at least two of the data elements gathered from the non-contiguous locations in the memory are packed and loaded into a single register file element of the register file entry.
摘要翻译：实施例涉及数据的打包加载和存储。一方面包括一种用于打包加载和存储分布在包括存储器和处理元件的系统中的数据的方法。该方法包括获取和解码由处理元件执行的指令。处理元件从存储器中的非连续位置收集多个可单独寻址的数据元素，该数据元素比基于指令的处理元件中的寄存器文件元素的标称宽度更窄。所述数据元素根据所述指令由所述处理元件打包并加载到寄存器文件条目的寄存器文件元素中，使得从存储器中的非连续位置收集的至少两个数据元素被打包并加载到注册文件条目的单个注册文件元素。

5. 发明授权

US09632778B2 Gather/scatter of multiple data elements with packed loading/storing into /from a register file entry 有权
公开(公告)号：US09632778B2
公开(公告)日：2017-04-25
申请号：US13569363
申请日：2012-08-08
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30036
摘要： Embodiments relate to packed loading and storing of data. An aspect includes a system for packed loading and storing of distributed data. The system includes memory and a processing element configured to communicate with the memory. The processing element is configured to perform a method including fetching and decoding an instruction for execution by the processing element. A plurality of individually addressable data elements is gathered from non-contiguous locations in the memory which are narrower than a nominal width of register file elements in the processing element based on the instruction. The processing element packs and loads the data elements into register file elements of a register file entry based on the instruction, such that at least two of the data elements gathered from the non-contiguous locations in the memory are packed and loaded into a single register file element of the register file entry.

6. 发明授权

US09632777B2 Gather/scatter of multiple data elements with packed loading/storing into/from a register file entry 有权
公开(公告)号：US09632777B2
公开(公告)日：2017-04-25
申请号：US13566141
申请日：2012-08-03
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30036
摘要： Embodiments relate to packed loading and storing of data. An aspect includes a method for packed loading and storing of data distributed in a system that includes memory and a processing element. The method includes fetching and decoding an instruction for execution by the processing element. The processing element gathers a plurality of individually addressable data elements from non-contiguous locations in the memory which are narrower than a nominal width of register file elements in the processing element based on the instruction. The data elements are packed and loaded into register file elements of a register file entry by the processing element based on the instruction, such that at least two of the data elements gathered from the non-contiguous locations in the memory are packed and loaded into a single register file element of the register file entry.

7. 发明授权

US07870341B2 Cache line replacement techniques allowing choice of LFU or MFU cache line replacement 有权
公开(公告)号：US07870341B2
公开(公告)日：2011-01-11
申请号：US12130245
申请日：2008-05-30
申请人： Richard Edward Matick , Jaime H. Moreno , Malcolm Scott Ware
发明人： Richard Edward Matick , Jaime H. Moreno , Malcolm Scott Ware
IPC分类号： G06F12/12
CPC分类号： H04W12/06 , G06F12/122 , G06F12/127 , H04L63/0853 , Y02D10/13
摘要： Methods and apparatus allowing a choice of Least Frequently Used (LFU) or Most Frequently Used (MFU) cache line replacement are disclosed. The methods and apparatus determine new state information for at least two given cache lines of a number of cache lines in a cache, the new state information based at least in part on prior state information for the at least two given cache lines. Additionally, when an access miss occurs in one of the at least two given lines, the methods and apparatus (1) select either LFU or MFU replacement criteria, and (2) replace one of the at least two given cache lines based on the new state information and the selected replacement criteria. Additionally, a cache for replacing MFU cache lines is disclosed. The cache additionally comprises MFU circuitry (1) adapted to produce new state information for the at least two given cache lines in response to an access to one of the at least two given cache lines, and (2) when a cache miss occurs in one of the at least two given cache lines, adapted to determine, based on the new state information, which of the at least two given cache lines is the most frequently used cache line.

8. 发明申请

US20090182951A1 CACHE LINE REPLACEMENT TECHNIQUES ALLOWING CHOICE OF LFU OR MFU CACHE LINE REPLACEMENT 有权
公开(公告)号：US20090182951A1
公开(公告)日：2009-07-16
申请号：US12130245
申请日：2008-05-30
申请人： Richard Edward Matick , Jaime H. Moreno , Malcolm Scott Ware
发明人： Richard Edward Matick , Jaime H. Moreno , Malcolm Scott Ware
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： H04W12/06 , G06F12/122 , G06F12/127 , H04L63/0853 , Y02D10/13
摘要： Methods and apparatus allowing a choice of Least Frequently Used (LFU) or Most Frequently Used (MFU) cache line replacement are disclosed. The methods and apparatus determine new state information for at least two given cache lines of a number of cache lines in a cache, the new state information based at least in part on prior state information for the at least two given cache lines. Additionally, when an access miss occurs in one of the at least two given lines, the methods and apparatus (1) select either LFU or MFU replacement criteria, and (2) replace one of the at least two given cache lines based on the new state information and the selected replacement criteria. Additionally, a cache for replacing MFU cache lines is disclosed. The cache additionally comprises MFU circuitry (1) adapted to produce new state information for the at least two given cache lines in response to an access to one of the at least two given cache lines, and (2) when a cache miss occurs in one of the at least two given cache lines, adapted to determine, based on the new state information, which of the at least two given cache lines is the most frequently used cache line.

9. 发明授权

US07051186B2 Selective bypassing of a multi-port register file 失效
标题翻译：选择性绕过多端口寄存器文件
公开(公告)号：US07051186B2
公开(公告)日：2006-05-23
申请号：US10230492
申请日：2002-08-29
申请人： Sameh Asaad , Jaime H. Moreno , Victor Zyuban
发明人： Sameh Asaad , Jaime H. Moreno , Victor Zyuban
IPC分类号： G06F15/82 , G06F9/305
CPC分类号： G06F9/3826 , G06F9/30109
摘要： A multi-port register file may be selectively bypassed such that any element in a result vector is bypassed to the same index of an input vector of a succeeding operation when the element is requested in the succeeding operation in the same index as it was generated. Alternatively, the results to be placed in a register file may be bypassed to a succeeding operation when the N elements that dynamically compose a vector are requested as inputs to the next operation exactly in the same order as they were generated. That is, for the purposes of bypassing, the N vector elements are treated as a single entity. Similar rules apply for the write-through path.
摘要翻译：可以选择性地旁路多端口寄存器文件，使得当在跟随生成的相同索引中在后续操作中请求元素时，结果向量中的任何元素被绕过到后续操作的输入向量的相同索引。或者，当动态组成向量的N个要素作为下一个操作的输入被精确地按照它们被生成的相同顺序被请求作为输入时，放置在寄存器文件中的结果可以被绕过到后续的操作。也就是说，为了绕过，N个向量元素被视为单个实体。类似的规则适用于直通路径。

10. 发明申请

US20090031084A1 CACHE LINE REPLACEMENT TECHNIQUES ALLOWING CHOICE OF LFU OR MFU CACHE LINE REPLACEMENT 有权
标题翻译：采用LFU或MFU高速缓存行替代方式的高速缓存行替换技术
公开(公告)号：US20090031084A1
公开(公告)日：2009-01-29
申请号：US12130278
申请日：2008-05-30
申请人： Richard Edward Matick , Jaime H. Moreno , Malcolm Scott Ware
发明人： Richard Edward Matick , Jaime H. Moreno , Malcolm Scott Ware
IPC分类号： G06F12/12
CPC分类号： H04W12/06 , G06F12/122 , G06F12/127 , H04L63/0853 , Y02D10/13
摘要： Methods and apparatus allowing a choice of Least Frequently Used (LFU) or Most Frequently Used (MFU) cache line replacement are disclosed. The methods and apparatus determine new state information for at least two given cache lines of a number of cache lines in a cache, the new state information based at least in part on prior state information for the at least two given cache lines. Additionally, when an access miss occurs in one of the at least two given lines, the methods and apparatus (1) select either LFU or MFU replacement criteria, and (2) replace one of the at least two given cache lines based on the new state information and the selected replacement criteria. Additionally, a cache for replacing MFU cache lines is disclosed. The cache additionally comprises MFU circuitry (1) adapted to produce new state information for the at least two given cache lines in response to an access to one of the at least two given cache lines, and (2) when a cache miss occurs in one of the at least two given cache lines, adapted to determine, based on the new state information, which of the at least two given cache lines is the most frequently used cache line.
摘要翻译：公开了允许选择最低频（LFU）或最常用（MFU）高速缓存线替换的方法和装置。所述方法和装置确定高速缓存中多个高速缓存行的至少两个给定高速缓存行的新状态信息，所述新状态信息至少部分地基于所述至少两个给定高速缓存行的先前状态信息。另外，当在至少两条给定行之一中存在访问错误时，方法和装置（1）选择LFU或MFU替换标准，以及（2）基于新的状态信息和所选择的替换标准。另外，公开了用于替换MFU高速缓存线的高速缓存。高速缓存还包括MFU电路（1），其适于响应于对至少两个给定高速缓存行中的一个的访问而产生用于所述至少两个给定高速缓存行的新状态信息，以及（2）当高速缓存未命中出现在一个所述至少两个给定高速缓存行适于基于所述新状态信息确定所述至少两个给定高速缓存行中的哪一个是最常用的高速缓存行。

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