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1. 发明授权

US6128674A Method of minimizing host CPU utilization in driving an adapter by residing in system memory a command/status block a soft interrupt block and a status block queue 失效
标题翻译：通过驻留在系统存储器中来最小化驱动适配器的主机CPU利用率的方法，命令/状态块软中断块和状态块队列
公开(公告)号：US6128674A
公开(公告)日：2000-10-03
申请号：US908888
申请日：1997-08-08
申请人： Bruce Leroy Beukema , Patrick Allen Buckland , Wen-Tzer Thomas Chen , David Arlen Elko , Ian David Judd , Renato John Recio
发明人： Bruce Leroy Beukema , Patrick Allen Buckland , Wen-Tzer Thomas Chen , David Arlen Elko , Ian David Judd , Renato John Recio
IPC分类号： G06F3/00 , G06F9/06 , G06F12/08 , G06F13/28
CPC分类号： G06F12/0835
摘要： The system I/O interface and its data structure are designed to minimize the host CPU utilization in driving an adapter. The interface is also designed to reduce the system interference in processing I/O requests. To eliminate the need of using PIO instructions, the command/status blocks for exchanging messages between the system and the adapter reside in the system memory. The data structure is designed to avoid "share write" entries in order to further minimize the overhead of maintaining each coherency when updating an entry in the cache either concurrently or sequentially by both adapter and system CPU. Further, the data structure of the control and status blocks is resided in the system memory. The system CPU uses STORE instruction to prepare control blocks and LOAD instruction to read from completion status blocks; while the adapter will rely on its DMA engine to move data to/from system memory in accessing control/status blocks.
摘要翻译：系统I / O接口及其数据结构旨在最大限度地减少驱动适配器时的主机CPU利用率。该接口还旨在减少处理I / O请求时的系统干扰。为了不需要使用PIO指令，系统和适配器之间交换消息的命令/状态块驻留在系统内存中。数据结构旨在避免“共享写入”条目，以便在适配器和系统CPU同时或顺序更新缓存中的条目时进一步最小化维护每个一致性的开销。此外，控制和状态块的数据结构驻留在系统存储器中。系统CPU使用STORE指令准备控制块和LOAD指令，从完成状态块读取; 而适配器将依靠其DMA引擎在访问控制/状态块时将数据移入/移出系统内存。

2. 发明授权

US5781897A Method and system for performing record searches in a database within a computer peripheral storage device 失效
标题翻译：用于在计算机外围存储设备内的数据库中执行记录搜索的方法和系统
公开(公告)号：US5781897A
公开(公告)日：1998-07-14
申请号：US634511
申请日：1996-04-18
申请人： Wen-Tzer Thomas Chen , Renato John Recio
发明人： Wen-Tzer Thomas Chen , Renato John Recio
IPC分类号： G06F17/30
CPC分类号： G06F17/30477 , G06F17/30492 , Y10S707/99933 , Y10S707/99934 , Y10S707/99935
摘要： A method for record searching in a database within a computer system are disclosed. The computer system includes a main processor, a main memory, and a peripheral storage device having a secondary processor. In accordance with the method of the present invention, a command block specifying a search string for record searching in at least one database table of the database is prepared. Subsequently, the command block is issued from the main processor to the secondary processor within the peripheral storage device of the computer system. The secondary processor within the peripheral storage device is then utilized to read the database table(s) into a memory within the peripheral storage device, in response to a receipt of the command block. The search string in the command block is compared to each record of the database table(s) within the memory of the peripheral storage device to identify all the records therein which contain the search string. Finally, all identified records which contain the search string are moved from the memory of the peripheral storage device to the main memory within the computer system, such that database record searching may be performed in a more efficient manner.
摘要翻译：公开了一种在计算机系统内的数据库中进行记录搜索的方法。计算机系统包括主处理器，主存储器和具有辅助处理器的外围存储设备。根据本发明的方法，准备在数据库的至少一个数据库表中指定用于记录搜索的搜索字符串的命令块。随后，命令块从计算机系统的外围存储设备中的主处理器发送到二级处理器。响应于接收到命令块，外围存储设备中的辅助处理器然后用于将数据库表读取到外围存储设备内的存储器中。将命令块中的搜索字符串与外围存储设备的存储器中的数据库表的每个记录进行比较，以识别其中包含搜索字符串的所有记录。最后，将包含搜索字符串的所有识别的记录从外围存储设备的存储器移动到计算机系统内的主存储器，使得可以以更有效的方式执行数据库记录搜索。

3. 发明授权

US6035418A System and method for improving resource utilization in a TCP/IP connection management system 失效
标题翻译：提高TCP / IP连接管理系统资源利用率的系统和方法
公开(公告)号：US6035418A
公开(公告)日：2000-03-07
申请号：US767242
申请日：1996-12-13
申请人： Renato John Recio , Wen-Tzer Thomas Chen
发明人： Renato John Recio , Wen-Tzer Thomas Chen
IPC分类号： G06F11/14
CPC分类号： G06F11/1443 , H04L1/1867
摘要： The present invention is a method and system for improving resource utilization in a connection management system. The present invention alleviates the resource contention and resource under-utilization problems, and avoids the problem of contamination from the late arrival of delayed packets to a new connection which utilizes the same resources used in a preview connection. The method includes transferring data by using the connection resources from the server; determining if an error occurred during the transfer of data; if an error is not detected, returning the connection resources to the server; and if an error is detected, indicating the existence of the error with a status bit and waiting a predetermined period of time prior to returning the connection resources to the server.
摘要翻译：本发明是一种提高连接管理系统的资源利用的方法和系统。本发明缓解了资源争用和资源利用不足问题，避免了延迟分组到达新的连接的污染问题，利用与预览连接相同的资源。该方法包括通过使用来自服务器的连接资源来传送数据; 确定在传输数据期间是否发生错误; 如果未检测到错误，则将连接资源返回到服务器; 并且如果检测到错误，则在将连接资源返回到服务器之前指示存在具有状态位的错误并等待预定时间段。

4. 发明授权

US08832416B2 Method and apparatus for instruction completion stall identification in an information handling system 有权
标题翻译：信息处理系统中指令完成失速识别的方法和装置
公开(公告)号：US08832416B2
公开(公告)日：2014-09-09
申请号：US11753005
申请日：2007-05-24
申请人： Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Alexander Erik Mericas , Mysore Sathyanarayana Srinivas
发明人： Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Alexander Erik Mericas , Mysore Sathyanarayana Srinivas
IPC分类号： G06F11/34
CPC分类号： G06F11/3409 , G06F11/3471 , G06F11/3476 , G06F2201/86 , G06F2201/865 , G06F2201/88 , G06F2201/885
摘要： An information handling system includes a processor that executes multiple instructions or instruction threads within a software application program. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In one embodiment, the operating system manages instruction completion stall analysis software to determine the cause or causes of instruction stalls. In another embodiment, the stall analysis software cooperates with the operating system software to store instruction completion stall event data on a per instruction basis while the application program executes. The operating system software may cooperate with the stall analysis software to store instruction completion stall data in memory for later manipulation by system users or other software.
摘要翻译：信息处理系统包括在软件应用程序内执行多个指令或指令线程的处理器。信息处理系统包括在多任务环境中管理处理器系统硬件和软件的操作系统软件。在一个实施例中，操作系统管理指令完成失速分析软件以确定指令停顿的原因或原因。在另一个实施例中，失速分析软件与操作系统软件配合，以在应用程序执行时以每个指令为基础存储指令完成失速事件数据。操作系统软件可以与失速分析软件配合以将指令完成失速数据存储在存储器中以供系统用户或其他软件稍后操作。

5. 发明授权

US07904870B2 Method and apparatus for integrated circuit design model performance evaluation using basic block vector clustering and fly-by vector clustering 有权
标题翻译：集成电路设计模型性能评估的方法和装置，采用基本的块矢量聚类和飞行矢量聚类
公开(公告)号：US07904870B2
公开(公告)日：2011-03-08
申请号：US12112035
申请日：2008-04-30
申请人： Robert H. Bell, Jr. , Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Pattabi Michael Seshadri , Madhavi Gopal Valluri
发明人： Robert H. Bell, Jr. , Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Pattabi Michael Seshadri , Madhavi Gopal Valluri
IPC分类号： G06F9/455
CPC分类号： G06F17/5022 , G01R31/318357 , G06F11/3428 , G06F11/3457 , G06F11/3664
摘要： A test system or simulator includes an enhanced IC test application sampling software program that executes test application software on a semiconductor die IC design model. The enhanced test application sampling software may include trace, simulation point, CPI error, clustering, instruction budgeting, and other programs. The enhanced test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software workloads. The enhanced test application sampling software utilizes the microarchitecture dependent information to generate the FBVs to select representative instruction intervals from the test application software. The enhanced test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing a global instruction budgeting analysis method. Designers use the test system with enhanced test application sampling software to evaluate IC design models by using the representative test application software program.
摘要翻译：测试系统或模拟器包括在半导体芯片IC设计模型上执行测试应用软件的增强型IC测试应用采样软件程序。增强的测试应用程序采样软件可能包括跟踪，模拟点，CPI错误，聚类，指令预算和其他程序。增强的测试应用采样软件从测试应用软件工作负载的指令跟踪分析中生成基本块向量（BBV）和飞越向量（FBV）。增强的测试应用采样软件利用微架构依赖信息生成FBV，以从测试应用软件中选择代表性指令间隔。增强的测试应用采样软件利用全球指令预算分析方法，从BBV和FBV数据生成代表性测试应用软件程序。设计人员使用带有增强型测试应用程序采样软件的测试系统，通过使用代表性的测试应用软件程序来评估IC设计模型。

6. 发明授权

US07814466B2 Method and apparatus for graphically marking instructions for instrumentation with hardware assistance 失效
标题翻译：用于以硬件帮助图形化标记仪器的方法和装置
公开(公告)号：US07814466B2
公开(公告)日：2010-10-12
申请号：US11381812
申请日：2006-05-05
申请人： Wen-Tzer Thomas Chen , Jimmie Earl DeWitt, Jr. , Frank Eliot Levine , Enio Manuel Pineda
发明人： Wen-Tzer Thomas Chen , Jimmie Earl DeWitt, Jr. , Frank Eliot Levine , Enio Manuel Pineda
IPC分类号： G06F9/44
CPC分类号： G06F11/348 , G06F11/3466 , G06F11/3612 , G06F2201/865 , G06F2201/88
摘要： A computer implemented method, apparatus and computer usable program code for marking instructions for instrumentation. A plurality of instructions is presented in a graphical user interface. A user input selecting a set of instructions in the plurality of instructions for instrumentation is received through the graphical user interface. A set of instructions is marked as a set of instrumentation instructions in response to receiving the user input. The set of instructions are executed by a processor if the processor is in an instrumentation mode, and the instrumentation instructions are unexecuted if an absence of the processor being in the instrumentation mode is present.
摘要翻译：计算机实现的方法，装置和计算机可用程序代码，用于标记仪器的指令。在图形用户界面中呈现多个指令。通过图形用户界面接收在多个用于仪器的指令中选择一组指令的用户输入。响应于接收到用户输入，一组指令被标记为一组仪器指令。如果处理器处于检测模式，那么指令集由处理器执行，并且如果处理器不在处于检测模式中，则仪器指令未执行。

7. 发明申请

US20090182994A1 TWO-LEVEL REPRESENTATIVE WORKLOAD PHASE DETECTION METHOD, APPARATUS, AND COMPUTER USABLE PROGRAM CODE 有权
标题翻译：两级代表性工作负载相位检测方法，装置和计算机可用程序代码
公开(公告)号：US20090182994A1
公开(公告)日：2009-07-16
申请号：US11972678
申请日：2008-01-11
申请人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Pattabi Michael Seshadri , Madhavi Gopal Valluri
发明人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Pattabi Michael Seshadri , Madhavi Gopal Valluri
IPC分类号： G06F9/30
CPC分类号： G06F11/3414 , G06F11/3476 , G06F2201/885
摘要： A method, apparatus, and computer-usable program code in a computer system for identifying a subset of a workload, which includes a total set of dynamic instructions, to use as a trace. Processor unit hardware executes the entire workload in real-time using a particular dataset. The processor unit hardware includes at least one microprocessor and at least one cache. The real-time execution of the workload is monitored to obtain information about how the processor unit hardware executes the workload when the workload is executed using the particular dataset to form actual performance information. Multiple different subsets of the workload are generated. The execution of each one of the subsets by the processor unit hardware is compared with the actual performance information. A result of the comparison is used to select one of the plurality of different subsets that roost closely represents the execution of the entire workload using the particular dataset to use as a trace.
摘要翻译：一种计算机系统中的方法，装置和计算机可用的程序代码，用于识别工作负载的子集，其包括一组动态指令，用作跟踪。处理器单元硬件使用特定数据集实时执行整个工作负载。处理器单元硬件包括至少一个微处理器和至少一个高速缓存。监视工作负载的实时执行，以获取有关当使用特定数据集执行工作负载以形成实际性能信息时处理器单元硬件如何执行工作负载的信息。生成多个不同的工作负载子集。将处理器单元硬件的每个子集的执行与实际的性能信息进行比较。比较的结果被用于选择多个不同的子集中的一个，这些子集中使用特定的数据集作为跟踪来密切地表示整个工作负荷的执行。

8. 发明授权

US06324612B1 Associating buffers in a bus bridge with corresponding peripheral devices to facilitate transaction merging 失效
标题翻译：将总线桥中的缓冲区与对应的外围设备相关联，以便于事务合并
公开(公告)号：US06324612B1
公开(公告)日：2001-11-27
申请号：US09210133
申请日：1998-12-10
申请人： Wen-Tzer Thomas Chen , Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Wen-Tzer Thomas Chen , Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1340
CPC分类号： G06F13/4059 , G06F13/4031
摘要： A bus bridge including a buffer pool and steering logic where the buffer pool is organized as a plurality of buffers sets including at least first and second buffer sets and the steering logic is adapted to store transactions originating with a first peripheral device in the first buffer set and transactions originating with a second peripheral device in the second buffer set. Transactions may arrive via a secondary bus, such as a PCI bus, coupled to the bus bridge. The bridge further allows relaxed transaction ordering rules compared to conventional PCI transaction ordering rules by identifying transactions by grant signals and thus allows steering of transactions from the first and second devices to first and second buffer sets respectively. The bridge is suitably adapted for combining or merging two or more transactions within each buffer set. Each buffer set preferably includes one or more buffers for temporarily storing transactions arriving from the secondary bus and bound for a primary bus. The primary bus may comprise a host bus connected to one or more processors or an additional PCI bus or other peripheral bus. The invention further contemplates a computer system including at least one processor, a bridge coupled to the processor via a host bus, and a plurality of peripheral devices including first and second peripheral devices coupled to the bridge via a secondary bus. In one embodiment, the bridge is configured to receive first and second request signals from the first and second peripheral devices respectively. The bridge preferably further includes arbitration logic for arbitrating mastership of the secondary bus in response to the request signals to produce first and second grant signals. The steering logic is suitably configured to utilize the first and second grant signals to determine the source of a subsequent transaction.
摘要翻译：一种包括缓冲池和转向逻辑的总线桥，其中所述缓冲池被组织为包括至少第一和第二缓冲器组的多个缓冲器组，并且所述转向逻辑适于将始发于第一外围设备的事务存储在所述第一缓冲器组中以及在第二缓冲器组中产生具有第二外围设备的交易。事务可以通过耦合到总线桥的辅助总线（诸如PCI总线）到达。与传统PCI事务排序规则相比，通过由授权信号识别事务并且因此允许将事务从第一和第二设备分别转向第一和第二缓冲器组，桥还允许轻松的事务排序规则。该桥适用于组合或合并每个缓冲区内的两个或多个事务。每个缓冲器组优选地包括一个或多个缓冲器，用于临时存储从次级总线到达并且被绑定到主总线的事务。主总线可以包括连接到一个或多个处理器或附加PCI总线或其他外围总线的主机总线。本发明进一步考虑了一种包括至少一个处理器，经由主机总线耦合到处理器的桥的计算机系统，以及包括通过次级总线耦合到桥接器的第一和第二外围设备的多个外围设备。在一个实施例中，桥被配置为分别从第一和第二外围设备接收第一和第二请求信号。桥接器优选地还包括用于响应于请求信号来仲裁辅助总线的主管以产生第一和第二授权信号的仲裁逻辑。转向逻辑被适当地配置为利用第一和第二授权信号来确定后续交易的来源。

9. 发明授权

US06301630B1 Interrupt response in a multiple set buffer pool bus bridge 失效
标题翻译：多组缓冲池总线桥中的中断响应
公开(公告)号：US06301630B1
公开(公告)日：2001-10-09
申请号：US09210127
申请日：1998-12-10
申请人： Wen-Tzer Thomas Chen , Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Wen-Tzer Thomas Chen , Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1300
CPC分类号： G06F13/4059
摘要： A bus bridge including a buffer pool comprised of a first and a second buffer sets. The first and second buffer sets are associated with first and second peripheral devices respectively. The bridge is configured to receive an interrupt and identify the interrupt source. A buffer set associated with the interrupt source is selected and transactions in the selected buffer set flushed prior to forwarding the interrupt to a processor. The bridge is preferably configured to identify the interrupt source by receiving a first interrupt signal from the first peripheral device and a second interrupt signal from the second peripheral device. Preferably, the bridge is configured to flush the transactions by pushing them into system memory via a primary bus such as a host bus of a processor. The invention further contemplates a system including a processor coupled to a host bus, a system memory, a bus bridge as described coupled between the host bus and a secondary bus, and first and second peripheral devices coupled to the secondary bus. Upon receiving an interrupt, the bridge is configured to identify the interrupt source, select a buffer set associated with the interrupt source, and flush posted memory write transactions in the selected buffer set, all prior to forwarding the interrupt to the processor. In one embodiment, the bridge, the first and second peripheral devices, and the secondary bus are compliant with the PCI specification. The bridge is configured in one embodiment to receive unique first and second interrupt signals from the first and second peripheral devices respectively.
摘要翻译：包括由第一和第二缓冲器组构成的缓冲池的总线桥。第一和第二缓冲器组分别与第一和第二外围设备相关联。桥接器配置为接收中断并识别中断源。选择与中断源关联的缓冲区，并将所选缓冲区中的事务刷新，然后再将中断转发给处理器。优选地，桥被配置为通过从第一外围设备接收第一中断信号和来自第二外围设备的第二中断信号来识别中断源。优选地，桥被配置为通过经由诸如处理器的主机总线的主总线将其推入系统存储器来刷新事务。本发明进一步考虑了一种系统，其包括耦合到主机总线的处理器，系统存储器，耦合在主机总线和辅助总线之间的总线桥，以及耦合到次级总线的第一和第二外围设备。在接收到中断时，桥被配置为识别中断源，选择与中断源相关联的缓冲区集合，以及在将中断转发到处理器之前清除所选缓冲区中的已发布的存储器写入事务。在一个实施例中，桥接器，第一和第二外围器件以及辅助总线符合PCI规范。在一个实施例中，桥被配置为分别从第一和第二外围设备接收唯一的第一和第二中断信号。

10. 发明授权

US5819083A Minimal sufficient buffer space for data redistribution in a parallel database system 失效
标题翻译：在并行数据库系统中用于数据重新分配的最小足够的缓冲区空间
公开(公告)号：US5819083A
公开(公告)日：1998-10-06
申请号：US116087
申请日：1993-09-02
申请人： Wen-Tzer Thomas Chen , Shih-Gong Li
发明人： Wen-Tzer Thomas Chen , Shih-Gong Li
IPC分类号： G06F17/30 , G06F15/163 , G06F13/14
CPC分类号： G06F17/30575
摘要： A method, system and program for distributing data to a first node in a parallel database system from a plurality of existing nodes. First, a minimal sufficient number of communication buffers necessary to guarantee that a table scan operation in each of the existing nodes will execute without stopping is determined. Once calculated, the minimal sufficient number of communication buffer is allocated in the memory associated with each of the existing nodes. Thus, data from each of the plurality of existing nodes to the first node can be redistributed without interruption. Unless the redistribution process has a default set of data to be redistributed, which data from which data tables in each of the plurality of existing nodes is to be distributed to the first node must be determined. The first node may either be a new node which must be registered within the parallel database system, or an existing node within an imbalanced parallel database system which has excess capacity. The minimal sufficient number of communication buffers is determined according to the ratio of a mean queuing in a communication buffer and an average time to fill a communication buffer.
摘要翻译：一种用于从多个现有节点向并行数据库系统中的第一节点分发数据的方法，系统和程序。首先，确定必要的最小足够数量的通信缓冲器，以保证在每个现有节点中的表扫描操作不停止地执行。一旦计算，在与每个现有节点相关联的存储器中分配最小足够数量的通信缓冲器。因此，可以不间断地重新分配从多个现有节点到第一节点的数据。除非再分配过程具有要重新分配的默认数据集，否则必须确定将多个现有节点中的每一个中的数据表从哪个数据表分发到第一个节点的数据。第一节点可以是必须在并行数据库系统中注册的新节点，或者具有过剩容量的不平衡并行数据库系统内的现有节点。根据通信缓冲器中的平均排队与填充通信缓冲器的平均时间的比率来确定最小数量的通信缓冲器。

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