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1. 发明授权

US06020639A Semiconductor wafer with removed CVD copper 失效
标题翻译：具有去除CVD铜的半导体晶片
公开(公告)号：US06020639A
公开(公告)日：2000-02-01
申请号：US223927
申请日：1998-12-31
申请人： Bruce Dale Ulrich , Tue Nguyen , Masato Kobayashi
发明人： Bruce Dale Ulrich , Tue Nguyen , Masato Kobayashi
IPC分类号： C23F1/02 , C23F1/18 , H01L21/304 , H01L21/306 , H01L21/3205 , H01L21/3213 , H01L23/48
CPC分类号： H01L21/32134 , C23F1/18 , H01L21/02063 , H01L21/02087 , H01L21/3212 , H01L21/6708
摘要： A method of using diluted nitric acid and an edge bead removal tool to remove copper from the perimeter of a semiconductor wafer is provided. In one embodiment, sensitive areas of the wafer are covered with photoresist, and the wafer perimeter cleared of photoresist, before the acid is applied. In another embodiment, sensitive areas of the wafer are protected with water spray as the copper etchant is applied. In a third embodiment, the nitric acid is applied to clear the wafer perimeter of copper before a chemical mechanical polishing (CMP) is performed on the layer of deposited copper. The excess thickness of copper protects copper interconnection structures from reacting with the copper etchant. All these methods permit copper to be removed at a low enough temperature that copper oxides are not formed. A semiconductor wafer cleaned of copper in accordance with the above-described method, and a system for low temperature copper removal is also provided.
摘要翻译：提供了使用稀硝酸和边缘珠除去工具从半导体晶片的周边去除铜的方法。在一个实施例中，在施加酸之前，晶片的敏感区域被光致抗蚀剂覆盖，并且晶片外围的光致抗蚀剂被清除。在另一个实施例中，当施加铜蚀刻剂时，晶片的敏感区域被水喷雾保护。在第三实施例中，在对沉积的铜层进行化学机械抛光（CMP）之前，施加硝酸以清除铜的晶片周边。铜的过剩厚度保护铜互连结构不与铜蚀刻剂反应。所有这些方法允许铜在没有形成铜氧化物的足够低的温度下被去除。还提供了根据上述方法清洁铜的半导体晶片和用于低温铜去除的系统。

2. 发明授权

US5897379A Low temperature system and method for CVD copper removal 失效
标题翻译：低温系统和CVD铜去除方法
公开(公告)号：US5897379A
公开(公告)日：1999-04-27
申请号：US995112
申请日：1997-12-19
申请人： Bruce Dale Ulrich , Tue Nguyen , Masato Kobayashi
发明人： Bruce Dale Ulrich , Tue Nguyen , Masato Kobayashi
IPC分类号： C23F1/02 , C23F1/18 , H01L21/304 , H01L21/306 , H01L21/3205 , H01L21/3213 , B44C1/22 , H01L21/308
CPC分类号： H01L21/32134 , C23F1/18 , H01L21/02063 , H01L21/02087 , H01L21/3212 , H01L21/6708
摘要： A method of using diluted nitric acid and an edge bead removal tool to remove copper from the perimeter of a semiconductor wafer is provided. In one embodiment, sensitive areas of the wafer are covered with photoresist, and the wafer perimeter cleared of photoresist, before the acid is applied. In another embodiment, sensitive areas of the wafer are protected with water spray as the copper etchant is applied. In a third embodiment, the nitric acid is applied to clear the wafer perimeter of copper before a chemical mechanical polishing (CMP) is performed on the layer of deposited copper. The excess thickness of copper protects copper interconnection structures from reacting with the copper etchant. All these methods permit copper to be removed at a low enough temperature that copper oxides are not formed. A semiconductor wafer cleaned of copper in accordance with the above-described method, and a system for low temperature copper removal is also provided.
摘要翻译：提供了使用稀硝酸和边缘珠除去工具从半导体晶片的周边去除铜的方法。在一个实施例中，在施加酸之前，晶片的敏感区域被光致抗蚀剂覆盖，并且晶片外围的光致抗蚀剂被清除。在另一个实施例中，当施加铜蚀刻剂时，晶片的敏感区域被水喷雾保护。在第三实施例中，在对沉积的铜层进行化学机械抛光（CMP）之前，施加硝酸以清除铜的晶片周边。铜的过剩厚度保护铜互连结构不与铜蚀刻剂反应。所有这些方法允许铜在没有形成铜氧化物的足够低的温度下被去除。还提供了根据上述方法清洁铜的半导体晶片和用于低温铜去除的系统。

3. 发明授权

US5936707A Multi-level reticle system and method for forming multi-level resist profiles 失效
标题翻译：多级掩模版系统及形成多层抗蚀剂型材的方法
公开(公告)号：US5936707A
公开(公告)日：1999-08-10
申请号：US8362
申请日：1998-01-16
申请人： Tue Nguyen , Bruce Dale Ulrich , David Russell Evans
发明人： Tue Nguyen , Bruce Dale Ulrich , David Russell Evans
IPC分类号： G03F1/00 , G03F1/29 , H01L21/469 , G03B27/00 , G03B27/04 , G03B27/28
CPC分类号： G03F1/29 , G03F1/50
摘要： A method is providing for making a multi-level reticle which transmits a plurality of incident light intensities, which in turn, are used to form a plurality of thicknesses in a photoresist profile. A partially transmitting film, used as one of the layers of the reticle, is able to provide an intermediate intensity light. The intermediate intensity light has an intensity approximately midway between the intensity of the unattenuated light passing through the reticle substrate layer, and the totally attenuated light blocked by an opaque layer of the reticle. The exposed photoresist receives light at two intensities to form a via hole in the resist in response to the higher intensity light, and a connecting line to the via at an intermediate level of the photoresist in response to the intermediate light intensity. A method for forming the multi-level resist profile from the multi-level reticle is provided as well as a multi-level reticle apparatus.
摘要翻译：一种提供制造多层掩模版的方法，其传输多个入射光强度，其又被用于在光致抗蚀剂轮廓中形成多个厚度。用作掩模版之一的部分透射膜能够提供中等强度的光。中间强度光在通过标线基底层的未衰减光的强度与由掩模版的不透明层阻挡的完全衰减的光之间的强度近似强度。暴露的光致抗蚀剂以两个强度接收光，以响应于较高强度的光而在抗蚀剂中形成通孔，以及响应于中间光强度而在光致抗蚀剂的中间水平处的通孔的连接线。提供了一种从多层掩膜形成多层抗蚀剂图案的方法以及多层掩模版设备。

4. 发明授权

US5906910A Multi-level photoresist profile method 失效
标题翻译：多层光刻胶轮廓法
公开(公告)号：US5906910A
公开(公告)日：1999-05-25
申请号：US8257
申请日：1998-01-16
申请人： Tue Nguyen , Bruce Dale Ulrich , David Russell Evans
发明人： Tue Nguyen , Bruce Dale Ulrich , David Russell Evans
IPC分类号： G03F1/00 , G03F1/29 , H01L21/469 , G03C5/00
CPC分类号： G03F1/29 , G03F1/50
摘要： A method is providing for making a multi-level reticle which transmits a plurality of incident light intensities, which in turn, are used to form a plurality of thicknesses in a photoresist profile. A partially transmitting film, used as one of the layers of the reticle, is able to provide an intermediate intensity light. The intermediate intensity light has an intensity approximately midway between the intensity of the unattenuated light passing through the reticle substrate layer, and the totally attenuated light blocked by an opaque layer of the reticle. The exposed photoresist receives light at two intensities to form a via hole in the resist in response to the higher intensity light, and a connecting line to the via at an intermediate level of the photoresist in response to the intermediate light intensity. A method for forming the multi-level resist profile from the multi-level reticle is provided as well as a multi-level reticle apparatus.
摘要翻译：一种提供制造多层掩模版的方法，其传输多个入射光强度，其又被用于在光致抗蚀剂轮廓中形成多个厚度。用作掩模版之一的部分透射膜能够提供中等强度的光。中间强度光在通过标线基底层的未衰减光的强度与由掩模版的不透明层阻挡的完全衰减的光之间的强度近似强度。暴露的光致抗蚀剂以两个强度接收光，以响应于较高强度的光而在抗蚀剂中形成通孔，以及响应于中间光强度而在光致抗蚀剂的中间水平处的通孔的连接线。提供了一种从多层掩膜形成多层抗蚀剂图案的方法以及多层掩模版设备。

5. 发明授权

US5914202A Method for forming a multi-level reticle 失效
标题翻译：形成多层掩模版的方法
公开(公告)号：US5914202A
公开(公告)日：1999-06-22
申请号：US660870
申请日：1996-06-10
申请人： Tue Nguyen , Bruce Dale Ulrich , David Russell Evans
发明人： Tue Nguyen , Bruce Dale Ulrich , David Russell Evans
IPC分类号： G03F1/00 , G03F1/29 , H01L21/469 , G03F9/00
CPC分类号： G03F1/29 , G03F1/50
摘要： A method is providing for making a multi-level reticle which transmits a plurality of incident light intensities, which in turn, are used to form a plurality of thicknesses in a photoresist profile. A partially transmitting film, used as one of the layers of the reticle, is able to provide an intermediate intensity of phase shifted light. The intermediate intensity light has an intensity approximately midway between the intensity of the unattenuated light passing through the reticle substrate layer, and the totally attenuated light blocked by an opaque layer of the reticle. The exposed photoresist receives light at two intensities to form a via hole in the resist in response to the higher intensity light, and a connecting line to the via at an intermediate level of the photoresist in response to the intermediate light intensity. A method for forming the multi-level resist profile from the multi-level reticle is provided as well as a multi-level reticle apparatus.
摘要翻译：一种提供制造多层掩模版的方法，其传输多个入射光强度，其又被用于在光致抗蚀剂轮廓中形成多个厚度。用作掩模版之一的部分透射膜能够提供相移光的中等强度。中间强度光在通过标线基底层的未衰减光的强度与由掩模版的不透明层阻挡的完全衰减的光之间的强度近似强度。暴露的光致抗蚀剂以两个强度接收光，以响应于较高强度的光而在抗蚀剂中形成通孔，以及响应于中间光强度而在光致抗蚀剂的中间水平处的通孔的连接线。提供了一种从多层掩膜形成多层抗蚀剂图案的方法以及多层掩模版设备。

6. 发明授权

US5821169A Hard mask method for transferring a multi-level photoresist pattern 失效
标题翻译：用于转印多层光刻胶图案的硬掩模方法
公开(公告)号：US5821169A
公开(公告)日：1998-10-13
申请号：US692379
申请日：1996-08-05
申请人： Tue Nguyen , Chien-Hsiung Peng , Bruce Dale Ulrich
发明人： Tue Nguyen , Chien-Hsiung Peng , Bruce Dale Ulrich
IPC分类号： H01L21/302 , G03F7/00 , H01L21/027 , H01L21/304 , H01L21/3065 , H01L21/311 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L21/00 , B44C1/22
CPC分类号： H01L21/76811 , G03F7/00 , H01L21/0274 , H01L21/31144 , H01L21/76802 , H01L21/76804 , H01L21/76813 , H01L2221/1021
摘要： A method is provided for forming intermediate levels in an integrated circuit dielectric during a damascene process using a hard mask layer to transfer the pattern of a photoresist mask having at least one intermediate thickness. The dielectric is covered with a hard mask layer, and the hard mask layer is covered with the photoresist mask. The photoresist mask pattern is transferred into the hard mask pattern so that the hard mask pattern has at least one intermediate thickness. The method forms an interconnect to a first depth in the dielectric through an opening in the hard mask pattern. The hard mask pattern is partially etched away in the area of the intermediate thickness to reveal a second dielectric surface area. The second dielectric surface area is etched to a second depth, less than the first depth. In this manner, vias can be formed to the first depth, and lines can be formed at a second depth to intersect the vias. The use of a relatively thin hard mask pattern reduces the degradation of vertical surface features, due to faceting, which generally occurs with the use of a thicker photoresist pattern. The method of the present invention allows a multi-level damascene process to be used to form features with relatively small geometries in the dielectric.
摘要翻译：提供一种用于在镶嵌工艺期间在集成电路电介质中形成中间层的方法，其中使用硬掩模层来传递具有至少一个中间厚度的光致抗蚀剂掩模的图案。电介质用硬掩模层覆盖，并且硬掩模层被光致抗蚀剂掩模覆盖。将光致抗蚀剂掩模图案转印到硬掩模图案中，使得硬掩模图案具有至少一个中间厚度。该方法通过硬掩模图案中的开口形成到电介质中的第一深度的互连。硬掩模图案在中间厚度的区域中被部分地蚀刻掉以露出第二电介质表面积。第二电介质表面积被蚀刻到比第一深度小的第二深度。以这种方式，可以将通孔形成为第一深度，并且可以在第二深度处形成线以与通孔相交。使用相对薄的硬掩模图案由于刻面而减少垂直表面特征的劣化，这通常通过使用较厚的光致抗蚀剂图案而发生。本发明的方法允许使用多层镶嵌工艺来形成电介质中具有较小几何形状的特征。

7. 发明授权

US6043164A Method for transferring a multi-level photoresist pattern 失效
标题翻译：转印多层光刻胶图案的方法
公开(公告)号：US6043164A
公开(公告)日：2000-03-28
申请号：US665014
申请日：1996-06-10
申请人： Tue Nguyen , Sheng Teng Hsu , Jer-shen Maa , Bruce Dale Ulrich , Chien-Hsiung Peng
发明人： Tue Nguyen , Sheng Teng Hsu , Jer-shen Maa , Bruce Dale Ulrich , Chien-Hsiung Peng
IPC分类号： G03F7/36 , H01L21/027 , H01L21/033 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/768
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76813 , H01L21/0274 , H01L21/0334 , H01L2221/1021
摘要： A method is provided for forming an intermediate level in an integrated circuit dielectric during a damascene process using a photoresist mask having an intermediate thickness. The method forms an interconnect to a first depth in the dielectric through an opening in the photoresist pattern. The photoresist profile is partially etched away in the area of the intermediate thickness to reveal a second dielectric surface area. The second dielectric surface area is then etched to a second depth less than the first depth. In this manner, vias can be formed to the first depth, and lines can be formed at a second depth to intersect the vias. The method of the present invention allows a dual damascene process to be performed with a single step of photoresist formation.
摘要翻译：提供一种用于在使用具有中间厚度的光致抗蚀剂掩模的镶嵌工艺期间在集成电路电介质中形成中间电平的方法。该方法通过光致抗蚀剂图案中的开口形成到电介质中的第一深度的互连。光致抗蚀剂轮廓在中间厚度的区域被部分地蚀刻掉以露出第二电介质表面积。然后将第二电介质表面积蚀刻到小于第一深度的第二深度。以这种方式，可以将通孔形成为第一深度，并且可以在第二深度处形成线以与通孔相交。本发明的方法允许通过单步形成光致抗蚀剂来进行双镶嵌工艺。

8. 发明授权

US07157111B2 MOCVD selective deposition of C-axis oriented PB5GE3O11 thin films on In2O3 oxides 有权
标题翻译： MOCVD选择性沉积C轴取向的PB5GE3O11薄膜在In2O3氧化物上
公开(公告)号：US07157111B2
公开(公告)日：2007-01-02
申请号：US10677007
申请日：2003-09-30
申请人： Tingkai Li , Sheng Teng Hsu , Bruce Dale Ulrich
发明人： Tingkai Li , Sheng Teng Hsu , Bruce Dale Ulrich
IPC分类号： B05D5/12 , C23C16/00
CPC分类号： C23C16/0272 , C23C16/40 , C23C16/56 , H01L21/02197 , H01L21/02205 , H01L21/02271 , H01L21/31691
摘要： A method of selectively depositing a ferroelectric thin film on an indium-containing substrate in a ferroelectric device includes preparing a silicon substrate; depositing an indium-containing thin film on the substrate; patterning the indium containing thin film; annealing the structure; selectively depositing a ferroelectric layer by MOCVD; annealing the structure; and completing the ferroelectric device.
摘要翻译：在铁电体元件的含铟基板上选择性地析出铁电薄膜的方法包括：制备硅基板; 在基板上沉积含铟薄膜; 图案化含铟薄膜; 退火结构; 通过MOCVD选择性沉积铁电层; 退火结构; 并完成铁电器件。

9. 发明授权

US5753417A Multiple exposure masking system for forming multi-level resist profiles 失效
标题翻译：用于形成多层抗蚀剂轮廓的多重曝光掩模系统
公开(公告)号：US5753417A
公开(公告)日：1998-05-19
申请号：US665013
申请日：1996-06-10
申请人： Bruce Dale Ulrich
发明人： Bruce Dale Ulrich
IPC分类号： H01L21/768 , G03F7/20 , H01L21/027 , G03F9/00
CPC分类号： G03F7/70066 , G03F7/2022 , G03F7/70466
摘要： A method is provided for forming multi-level profiles from a photoresist mask. The method includes exposing selected areas of a photoresist layer to two or more different patterns of light at different light dosage levels. For example, one pattern will be exposed to a relatively low dose of light, or to light for a short duration, and a second pattern will be exposed to a relatively high dose of light, or for a greater duration. The plurality of different exposures at different dosage levels occur prior to developing the photoresist. When the photoresist layer is developed, the pattern exposed to a lower dose of light will be etched substantially more slowly than the areas of the photoresist exposed to higher dose of light. By controlling the development process to completely remove the resist in the areas exposed to a high dose of light and only partially remove the resist in the areas exposed to a lower dose of light, a multi-level photoresist profile is formed. Such a multi-level profile can then be used in subsequent semiconductor processing, for example, the formation of interconnects and vias.
摘要翻译：提供了一种从光致抗蚀剂掩模形成多层轮廓的方法。该方法包括将光致抗蚀剂层的选定区域暴露于不同光剂量水平的两种或更多种不同的光模式。例如，一种图案将暴露于相对低剂量的光，或者在短时间内照射，并且第二图案将暴露于相对高剂量的光或更长的持续时间。不同剂量水平下的多种不同曝光在显影光致抗蚀剂之前发生。当光致抗蚀剂层被显影时，暴露于较低剂量的光的图案将比暴露于较高剂量的光的光刻胶的区域蚀刻得更加缓慢。通过控制显影处理以在暴露于高剂量的光的区域中完全去除抗蚀剂，并且仅部分地去除暴露于较低剂量的光的区域中的抗蚀剂，形成多层光致抗蚀剂轮廓。然后可以在随后的半导体处理中使用这样的多层次轮廓，例如互连和通孔的形成。

10. 发明授权

US07053001B2 Selective etching processes for In2O3 thin films in FeRAM device applications 有权
标题翻译： FeRAM器件应用中In2O3薄膜的选择性蚀刻工艺
公开(公告)号：US07053001B2
公开(公告)日：2006-05-30
申请号：US10676983
申请日：2003-09-30
申请人： Tingkai Li , Sheng Teng Hsu , Bruce Dale Ulrich
发明人： Tingkai Li , Sheng Teng Hsu , Bruce Dale Ulrich
IPC分类号： H01I21/302
CPC分类号： H01L21/31122 , H01L21/28291 , H01L21/2855 , H01L21/32051
摘要： A method of selective etching a metal oxide layer for fabrication of a ferroelectric device includes preparing a silicon substrate, including forming an oxide layer thereon; depositing a layer of metal or metal oxide thin film on the substrate; patterning and selectively etching the metal or metal oxide thin film without substantially over etching into the underlying oxide layer; depositing a layer of ferroelectric material; depositing a top electrode on the ferroelectric material; and completing the ferroelectric device.
摘要翻译：选择性蚀刻用于制造铁电体器件的金属氧化物层的方法包括制备硅衬底，包括在其上形成氧化物层; 在衬底上沉积一层金属或金属氧化物薄膜; 图案化和选择性地蚀刻金属或金属氧化物薄膜，而基本上不会过度蚀刻到下面的氧化物层中; 沉积一层铁电材料; 在铁电材料上沉积顶部电极; 并完成铁电器件。

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