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1. 发明申请

US20040240559A1 Context adaptive binary arithmetic code decoding engine 失效
标题翻译：上下文自适应二进制算术码解码引擎
公开(公告)号：US20040240559A1
公开(公告)日：2004-12-02
申请号：US10854592
申请日：2004-05-26
申请人： Broadcom Corporation
发明人： Ramkumar Prakasam , Alexander G. MacInnis , Olive Tao , Xiaodong Xie
IPC分类号： H04N007/12
CPC分类号： H04N19/42 , H04N19/44 , H04N19/91
摘要： A CABAC decoding engine is devised to cover all aspects of decoding all CABAC-coded syntax elements for AVC. This CABAC decoding engine acts like a Co-processor to another Processor (CPU), which guides the decoding of the bit stream. The CABAC decoding engine or Co-processor has the following highlights: unique context model retrieving and storing method is developed to allow a complete syntax element to be decoded in one hardware (H/W) execution cycle (not necessarily one clock cycle.); H/W assisted approach is provided to accelerate context model initialization; H/W based approach is incorporated to allow fast de-binarization; H/W based approach is provided to allow a block of syntax elements to be decoded instead of one by one; and dedicated H/W accelerators are incorporated to decode special syntax elements.
摘要翻译： CABAC解码引擎被设计为涵盖对AVC的所有CABAC编码语法元素进行解码的所有方面。该CABAC解码引擎像另一个处理器（CPU）的Co处理器一样起作用，它引导了位流的解码。 CABAC解码引擎或协处理器具有以下亮点：开发独特的上下文模型检索和存储方法，以允许在一个硬件（H / W）执行周期（不一定是一个时钟周期）对完整的语法元素进行解码。提供H / W辅助方法来加速上下文模型初始化; 并入基于H / W的方法可实现快速去二值化; 提供基于H / W的方法以允许一个语法元素块被逐个解码; 并集成专用H / W加速器来解码特殊的语法元素。

2. 发明申请

US20040150652A1 Graphics display system with window descriptors 有权
公开(公告)号：US20040150652A1
公开(公告)日：2004-08-05
申请号：US10762937
申请日：2004-01-21
申请人： Broadcom Corporation
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G09G005/02
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip uses window descriptors to describe logical surfaces, or windows, of graphics information to be displayed on the screen. The chip incorporates a unified memory architecture that provides a high level of system performance while conserving memory bandwidth and chip size. Video and graphics scaling capabilities as well as anti-flutter filtering capability are provided.

3. 发明申请

US20040130558A1 Apparatus and method for blending graphics and video surfaces 有权
标题翻译：用于混合图形和视频表面的装置和方法
公开(公告)号：US20040130558A1
公开(公告)日：2004-07-08
申请号：US10712809
申请日：2003-11-13
申请人： Broadcom Corporation
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G09G005/00
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip blends graphics and video information by various graphics windows using alpha values for the windows, alpha values per pixel, or both. The chip calculates a composite alpha value based on the window's alpha values and the alpha values per pixel. Blended graphics and video may then be composited using the composite alpha value.
摘要翻译：在用于控制电视显示器的机顶盒中使用图形集成电路芯片。图形芯片处理模拟视频输入，数字视频输入和图形输入。该芯片通过各种图形窗口混合图形和视频信息，使用窗口的Alpha值，每像素的Alpha值或两者。芯片根据窗口的alpha值和每像素的alpha值计算复合Alpha值。混合图形和视频可以使用复合alpha值进行合成。

4. 发明申请

US20030206174A1 Graphics display system with line buffer control scheme 失效
公开(公告)号：US20030206174A1
公开(公告)日：2003-11-06
申请号：US10423364
申请日：2003-04-25
申请人： Broadcom Corporation
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiadong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G06F001/12 , H04L005/00 , H04L007/00 , G06F013/42 , G09G005/36
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The system includes plurality of line buffers for receiving the graphics contents. The graphics contents are composited into each of the plurality of line buffers by blending the graphics contents with the existing contents of the line buffer until all of the graphics surfaces for the line have been composited.

5. 发明申请

US20040212734A1 Graphics display system with video synchronization feature 有权
公开(公告)号：US20040212734A1
公开(公告)日：2004-10-28
申请号：US10847122
申请日：2004-05-17
申请人： Broadcom Corporation
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： H04N005/04
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. The system includes a video decoder having a chroma-locked sample rate converter. The chroma-locked sample rate converter converts the samples to those taken at a sample rate that is a multiple of the chroma subcarrier frequency and that is locked to chroma bursts of the analog video signal in a control loop. The video decoder also includes a line-locked sample rate converter that receives samples at a multiple of the chroma subcarrier frequency and converts the samples to samples with a sample frequency that is a multiple of the horizontal line rate of the video input. The line-locked sample rate converter measures the horizontal line rate to an accuracy of a fraction of a pixel and adjusts the sample rate and phase of the line-locked sample rate converter to produce accurate line-locked samples. The time base corrector receives samples at the output of the line-locked sample rate converter and provides samples synchronized to the display clock for reducing undesirable artifacts such as jitter.

6. 发明申请

US20040177191A1 Graphics display system with unified memory architecture 有权
标题翻译：图形显示系统具有统一的内存架构
公开(公告)号：US20040177191A1
公开(公告)日：2004-09-09
申请号：US10763087
申请日：2004-01-22
申请人： Broadcom Corporation
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G06F012/00 , G06F013/14 , G06F013/38
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.
摘要翻译：在用于控制电视显示器的机顶盒中使用图形显示系统集成电路。图形显示系统处理模拟视频输入，数字视频输入和图形输入。该系统包含由图形系统，CPU和其他外围设备共享的统一存储器架构。统一存储器架构使用实时调度来服务任务。关键瞬时分析用于查找不影响实时任务的内存需求的内存使用计划，同时根据需要为非实时任务进行服务。

7. 发明申请

US20030158987A1 Graphics display system with unified memory architecture 有权
公开(公告)号：US20030158987A1
公开(公告)日：2003-08-21
申请号：US10322059
申请日：2002-12-17
申请人： Broadcom Corporation
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G06F013/14 , G06F013/38 , G06F012/00
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

8. 发明申请

US20040208245A1 Video and graphics system with video scaling 有权
公开(公告)号：US20040208245A1
公开(公告)日：2004-10-21
申请号：US10843657
申请日：2004-05-11
申请人： Broadcom Corporation
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Vivian Hsiun
IPC分类号： H04N007/12
CPC分类号： H04N9/641 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/128 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N5/46 , H04N7/0135 , H04N9/45 , H04N11/143 , H04N11/20 , H04N21/42653 , H04N21/42692 , H04N21/4305 , H04N21/4307 , H04N21/4316 , H04N21/4347 , H04N21/440218 , H04N21/44029
摘要： A video and graphics system has a reduced memory mode in which video images are reduced in half in horizontal direction during decoding. The video and graphics system includes a video decoder for decoding MPEG-2 video data. The video images may not be downscaled in the horizontal direction when no bi-directionally predicted pictures are used. The video and graphics system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format. The output having an SDTV format may be recorded using a video cassette recorder (VCR) while the HDTV video is being displayed.

9. 发明申请

US20040207644A1 Graphics display system with anti-flutter filtering and vertical scaling feature 有权
公开(公告)号：US20040207644A1
公开(公告)日：2004-10-21
申请号：US10842743
申请日：2004-05-10
申请人： Broadcom Corporation
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G09G005/00
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

10. 发明申请

US20040177190A1 Graphics display system with unified memory architecture 有权
公开(公告)号：US20040177190A1
公开(公告)日：2004-09-09
申请号：US10762975
申请日：2004-01-22
申请人： Broadcom Corporation
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G06F012/00 , G06F013/14 , G06F013/38
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

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