专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08030197B2 Recessed channel array transistor (RCAT) in replacement metal gate (RMG) logic flow 有权
标题翻译：嵌入式通道阵列晶体管（RCAT）在替代金属栅极（RMG）逻辑流
公开(公告)号：US08030197B2
公开(公告)日：2011-10-04
申请号：US12435382
申请日：2009-05-04
申请人： Brian S. Doyle , Gilbert Dewey , Ravi Pillarisetty , Nick Lindert , Uday Shah , Dinesh Somasekhar
发明人： Brian S. Doyle , Gilbert Dewey , Ravi Pillarisetty , Nick Lindert , Uday Shah , Dinesh Somasekhar
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823456 , H01L21/82345 , H01L21/823462 , H01L29/4236 , H01L29/49 , H01L29/51 , H01L29/66545 , H01L29/66583 , H01L29/66621 , H01L29/7833 , H01L29/7834
摘要： Embodiments of the invention relate to a method of fabricating logic transistors using replacement metal gate (RMG) logic flow with modified process to form recessed channel array transistors (RCAT) on a common semiconductor substrate. An embodiment comprises forming an interlayer dielectric (ILD) layer on a semiconductor substrate, forming a first recess in the ILD layer of a first substrate region, forming a recessed channel in the ILD layer and in the substrate of a second substrate region, depositing a first conformal high-k dielectric layer in the first recess and a second conformal high-k dielectric layer in the recessed channel, and filling the first recess with a first gate metal and the recessed channel with a second gate metal.
摘要翻译：本发明的实施例涉及使用具有修改过程的替代金属栅（RMG）逻辑流来制造逻辑晶体管的方法，以在公共半导体衬底上形成凹陷沟道阵列晶体管（RCAT）。一个实施例包括在半导体衬底上形成层间绝缘层（ILD）层，在第一衬底区域的ILD层中形成第一凹槽，在第一衬底区域的ILD层和衬底中形成凹陷沟道，第一凹部中的第一共形高k电介质层和凹陷沟道中的第二共形高k电介质层，并且用第一栅极金属填充第一凹槽，并且利用第二栅极金属填充凹陷沟道。

2. 发明申请

US20100276757A1 RECESSED CHANNEL ARRAY TRANSISTOR (RCAT) IN REPLACEMENT METAL GATE (RMG) LOGIC FLOW 有权
标题翻译：更换金属门（RMG）中的后续通道阵列晶体管（RCAT）逻辑流
公开(公告)号：US20100276757A1
公开(公告)日：2010-11-04
申请号：US12435382
申请日：2009-05-04
申请人： Brian S. Doyle , Gilbert Dewey , Ravi Pillarisetty , Nick Lindert , Uday Shah , Dinesh Somasekhar
发明人： Brian S. Doyle , Gilbert Dewey , Ravi Pillarisetty , Nick Lindert , Uday Shah , Dinesh Somasekhar
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823456 , H01L21/82345 , H01L21/823462 , H01L29/4236 , H01L29/49 , H01L29/51 , H01L29/66545 , H01L29/66583 , H01L29/66621 , H01L29/7833 , H01L29/7834
摘要： Embodiments of the invention relate to a method of fabricating logic transistors using replacement metal gate (RMG) logic flow with modified process to form recessed channel array transistors (RCAT) on a common semiconductor substrate. An embodiment comprises forming an interlayer dielectric (ILD) layer on a semiconductor substrate, forming a first recess in the ILD layer of a first substrate region, forming a recessed channel in the ILD layer and in the substrate of a second substrate region, depositing a first conformal high-k dielectric layer in the first recess and a second conformal high-k dielectric layer in the recessed channel, and filling the first recess with a first gate metal and the recessed channel with a second gate metal.
摘要翻译：本发明的实施例涉及使用具有修改过程的替代金属栅（RMG）逻辑流来制造逻辑晶体管的方法，以在公共半导体衬底上形成凹陷沟道阵列晶体管（RCAT）。一个实施例包括在半导体衬底上形成层间绝缘层（ILD）层，在第一衬底区域的ILD层中形成第一凹槽，在第一衬底区域的ILD层和衬底中形成凹陷沟道，第一凹部中的第一共形高k电介质层和凹陷沟道中的第二共形高k电介质层，并且用第一栅极金属填充第一凹槽，并且利用第二栅极金属填充凹陷沟道。

3. 发明申请

US20110260244A1 RECESSED CHANNEL ARRAY TRANSISTOR (RCAT) IN REPLACEMENT METAL GATE (RMG) LOGIC FLOW 审中-公开
标题翻译：更换金属门（RMG）中的后续通道阵列晶体管（RCAT）逻辑流
公开(公告)号：US20110260244A1
公开(公告)日：2011-10-27
申请号：US13178974
申请日：2011-07-08
申请人： Brian S. Doyle , Gilbert Dewey , Ravi Pillarisetty , Nick Lindert , Uday Shah , Dinesh Somasekhar
发明人： Brian S. Doyle , Gilbert Dewey , Ravi Pillarisetty , Nick Lindert , Uday Shah , Dinesh Somasekhar
IPC分类号： H01L27/092
CPC分类号： H01L21/823456 , H01L21/82345 , H01L21/823462 , H01L29/4236 , H01L29/49 , H01L29/51 , H01L29/66545 , H01L29/66583 , H01L29/66621 , H01L29/7833 , H01L29/7834
摘要： Embodiments of the invention relate to a method of fabricating logic transistors using replacement metal gate (RMG) logic flow with modified process to form recessed channel array transistors (RCAT) on a common semiconductor substrate. An embodiment comprises forming an interlayer dielectric (ILD) layer on a semiconductor substrate, forming a first recess in the ILD layer of a first substrate region, forming a recessed channel in the ILD layer and in the substrate of a second substrate region, depositing a first conformal high-k dielectric layer in the first recess and a second conformal high-k dielectric layer in the recessed channel, and filling the first recess with a first gate metal and the recessed channel with a second gate metal.
摘要翻译：本发明的实施例涉及使用具有修改过程的替代金属栅（RMG）逻辑流来制造逻辑晶体管的方法，以在公共半导体衬底上形成凹陷沟道阵列晶体管（RCAT）。一个实施例包括在半导体衬底上形成层间绝缘层（ILD）层，在第一衬底区域的ILD层中形成第一凹槽，在第一衬底区域的ILD层和衬底中形成凹陷沟道，第一凹部中的第一共形高k电介质层和凹陷沟道中的第二共形高k电介质层，并且用第一栅极金属填充第一凹槽，并且利用第二栅极金属填充凹陷沟道。

4. 发明申请

US20120235274A1 SEMICONDUCTOR STRUCTURE HAVING AN INTEGRATED DOUBLE-WALL CAPACITOR FOR EMBEDDED DYNAMIC RANDOM ACCESS MEMORY (EDRAM) AND METHOD TO FORM THE SAME 审中-公开
标题翻译：具有用于嵌入式动态随机存取存储器（EDRAM）的集成双壁电容器的半导体结构及其形成方法
公开(公告)号：US20120235274A1
公开(公告)日：2012-09-20
申请号：US13047656
申请日：2011-03-14
申请人： Brian S. Doyle , Charles C. Kuo , Nick Lindert , Uday Shah , Satyarth Suri , Robert S. Chau
发明人： Brian S. Doyle , Charles C. Kuo , Nick Lindert , Uday Shah , Satyarth Suri , Robert S. Chau
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L27/10894 , H01L27/10817 , H01L27/10855 , H01L28/91
摘要： Semiconductor structures having integrated double-wall capacitors for eDRAM and methods to form the same are described. For example, an embedded double-wall capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. The trench has a bottom and sidewalls. A U-shaped metal plate is disposed at the bottom of the trench, spaced apart from the sidewalls. A second dielectric layer is disposed on and conformal with the sidewalls of the trench and the U-shaped metal plate. A top metal plate layer is disposed on and conformal with the second dielectric layer.
摘要翻译：描述了具有用于eDRAM的集成双壁电容器的半导体结构及其形成方法。例如，嵌入式双壁电容器包括设置在设置在基板上方的第一电介质层中的沟槽。沟槽有一个底部和侧壁。 U形金属板设置在沟槽的底部，与侧壁间隔开。第二电介质层设置在沟槽和U形金属板的侧壁上并与其一致。顶部金属板层设置在第二介电层上并与第二介质层保形。

5. 发明授权

US07763943B2 Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin 有权
标题翻译：通过结合部分金属翅片来减少多栅极器件的外部电阻
公开(公告)号：US07763943B2
公开(公告)日：2010-07-27
申请号：US11964623
申请日：2007-12-26
申请人： Ravi Pillarisetty , Uday Shah , Titash Rakshit , Jack T. Kavalieros , Brian S. Doyle
发明人： Ravi Pillarisetty , Uday Shah , Titash Rakshit , Jack T. Kavalieros , Brian S. Doyle
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/785 , H01L29/66795
摘要： Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin is generally described. In one example, an apparatus includes a semiconductor substrate and one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions where the gate region of the one or more fins includes a semiconductor material and where the source and drain regions of the one or more fins include a metal portion and a semiconductor portion, the metal portion and the semiconductor portion being coupled together.
摘要翻译：通常描述通过结合部分金属翅片来降低多栅极器件的外部电阻。在一个示例中，设备包括半导体衬底和与半导体衬底耦合的多栅极晶体管器件的一个或多个鳍片，该一个或多个鳍片具有栅极区域，源极区域和漏极区域，栅极区域设置在源极和漏极区域之间，其中一个或多个鳍片的栅极区域包括半导体材料，并且其中一个或多个鳍片的源极和漏极区域包括金属部分和半导体部分，金属部分和半导体部分联接在一起。

6. 发明授权

US08030163B2 Reducing external resistance of a multi-gate device using spacer processing techniques 有权
标题翻译：使用间隔物处理技术降低多栅极器件的外部电阻
公开(公告)号：US08030163B2
公开(公告)日：2011-10-04
申请号：US11964593
申请日：2007-12-26
申请人： Ravi Pillarisetty , Uday Shah , Brian S. Doyle , Jack T. Kavalieros
发明人： Ravi Pillarisetty , Uday Shah , Brian S. Doyle , Jack T. Kavalieros
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/66545 , H01L29/785
摘要： A method includes depositing a sacrificial gate electrode to one or more multi-gate fins. The sacrificial gate electrode is patterned such that it is coupled to a gate region and substantially no sacrificial gate electrode is coupled to source and drain regions. A dielectric film is formed that is coupled to the source and drain regions. The sacrificial gate electrode is removed and a spacer gate dielectric is deposited to the gate region wherein substantially no spacer gate dielectric is deposited to the source and drain regions. The spacer gate dielectric is etched to completely remove the spacer gate dielectric from the gate region area that is to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric that is to be coupled with the final gate electrode that remains coupled with the dielectric film.
摘要翻译：一种方法包括将牺牲栅电极沉积到一个或多个多栅极散热片上。牺牲栅电极被图案化，使得它被耦合到栅极区域，并且基本上没有牺牲栅极电极耦合到源极和漏极区域。形成了与源极和漏极区域耦合的电介质膜。牺牲栅极电极被去除，并且间隔栅极电介质沉积到栅极区域，其中基本上没有间隔栅极电介质沉积到源区和漏极区。蚀刻间隔栅极电介质以完全去除要与最终栅电极耦合的栅极区域的间隔栅极电介质，除了与最终栅电极耦合的间隔栅极电介质的剩余预定厚度之外，保持与电介质膜耦合。

7. 发明申请

US20150091067A1 HYBRID PHASE FIELD EFFECT TRANSISTOR 有权
标题翻译：混合相位效应晶体管
公开(公告)号：US20150091067A1
公开(公告)日：2015-04-02
申请号：US14040574
申请日：2013-09-27
申请人： Ravi Pillarisetty , Brian S. Doyle , Elijah V. Karpov , David L. Kencke , Uday Shah , Charles C. Kuo , Robert S. Chau
发明人： Ravi Pillarisetty , Brian S. Doyle , Elijah V. Karpov , David L. Kencke , Uday Shah , Charles C. Kuo , Robert S. Chau
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L27/2436 , H01L29/66477 , H01L29/66568 , H01L29/66795 , H01L29/78 , H01L29/785 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L2029/7858
摘要： An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.
摘要翻译：在晶体管结构上沉积绝缘层。晶体管结构包括位于衬底上的器件层上的栅电极。晶体管结构包括在栅电极的相对侧的器件层上的第一接触区域和第二接触区域。在第一接触区域上的第一绝缘层中形成沟槽。具有S形IV特性的金属 - 绝缘体相变材料层沉积在源极侧上方的金属化层的沟槽或通路中。

8. 发明申请

US20110284965A1 REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE USING SPACER PROCESSING TECHNIQUES 审中-公开
标题翻译：使用间隔加工技术降低多门装置的外部电阻
公开(公告)号：US20110284965A1
公开(公告)日：2011-11-24
申请号：US13204987
申请日：2011-08-08
申请人： Ravi Pillarisetty , Uday Shah , Brian S. Doyle , Jack T. Kavalieros
发明人： Ravi Pillarisetty , Uday Shah , Brian S. Doyle , Jack T. Kavalieros
IPC分类号： H01L29/78
CPC分类号： H01L29/66795 , H01L29/66545 , H01L29/785
摘要： Reducing external resistance of a multi-gate device using spacer processing techniques is generally described. In one example, a method includes depositing a sacrificial gate electrode to one or more multi-gate fins, the one or more multi-gate fins comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, patterning the sacrificial gate electrode such that the sacrificial gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins, forming a dielectric film coupled to the source and drain regions of the one or more multi-gate fins, removing the sacrificial gate electrode from the gate region of the one or more to multi-gate fins, depositing spacer gate dielectric to the gate region of the one or more multi-gate fins wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film, and etching the spacer gate dielectric to completely remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film.
摘要翻译：通常描述使用间隔物处理技术降低多栅极器件的外部电阻。在一个示例中，一种方法包括将牺牲栅电极沉积到一个或多个多栅极散热片上，一个或多个多栅极鳍片包括栅极区域，源极区域和漏极区域，栅极区域设置在源极和漏极区域，图案化牺牲栅极电极，使得牺牲栅电极材料耦合到栅极区域，并且基本上没有牺牲栅极电极耦合到一个或多个多栅极鳍片的源极和漏极区域，形成电介质将一个或多个多栅极翅片的源极和漏极区域耦合到所述一个或多个多栅极散热片的栅极区域;将所述牺牲栅极电极从所述一个或多个至多个栅极鳍片的栅极区域移除;将间隔栅极电介质沉积到所述一个或多个栅极栅极栅极区域; 更多的多栅极鳍片，其中基本上没有间隔栅极电介质沉积到一个或多个多栅极鳍片的源极和漏极区域，源极和漏极区域被电介质保护膜和蚀刻间隔栅极电介质以从栅极区域区域完全去除间隔栅极电介质，以与最终栅极电极耦合，除了与保持耦合的最终栅电极耦合的间隔栅极电介质的剩余预定厚度之外与电介质膜。

9. 发明授权

US07825437B2 Unity beta ratio tri-gate transistor static random access memory (SRAM) 有权
标题翻译：统一beta比三栅晶体管静态随机存取存储器（SRAM）
公开(公告)号：US07825437B2
公开(公告)日：2010-11-02
申请号：US12006082
申请日：2007-12-28
申请人： Ravi Pillarisetty , Suman Datta , Jack Kavalieros , Brian S. Doyle , Uday Shah
发明人： Ravi Pillarisetty , Suman Datta , Jack Kavalieros , Brian S. Doyle , Uday Shah
IPC分类号： H01L27/118
CPC分类号： H01L27/1104 , H01L27/11
摘要： In general, in one aspect, a method includes forming N-diffusion and P-diffusion fins in a semiconductor substrate. A P-diffusion gate layer is formed over the semiconductor substrate and removed from the N-diffusion fins. A pass-gate N-diffusion gate layer is formed over the semiconductor substrate and removed from the P-diffusion fins and pull-down N-diffusion fins. A pull-down N-diffusion layer is formed over the semiconductor substrate.
摘要翻译：通常，在一个方面，一种方法包括在半导体衬底中形成N-扩散和P-扩散翅片。在半导体衬底上形成P扩散栅极层，并从N扩散鳍片上去除。在半导体衬底上形成通过栅极的N扩散栅极层，并从P扩散鳍片和下拉的N扩散鳍片中去除。在半导体衬底上形成下拉式N扩散层。

10. 发明授权

US07820512B2 Spacer patterned augmentation of tri-gate transistor gate length 有权
标题翻译：三栅极晶体管栅极长度的间隔图案化扩充
公开(公告)号：US07820512B2
公开(公告)日：2010-10-26
申请号：US12006063
申请日：2007-12-28
申请人： Ravi Pillarisetty , Suman Datta , Jack Kavalieros , Brian S. Doyle , Uday Shah
发明人： Ravi Pillarisetty , Suman Datta , Jack Kavalieros , Brian S. Doyle , Uday Shah
IPC分类号： H01L21/8234 , H01L21/336 , H01L21/311
CPC分类号： H01L27/1104 , H01L27/0207
摘要： In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the semiconductor substrate. A gate electrode hard mask is formed over the gate stack. The gate electrode hard mask is augmented around pass gate transistors with a spacer material. The gate stack is etched using the augmented gate electrode hard mask to form the gate electrodes. The gate electrodes around the pass gate have a greater length than other gate electrodes.
摘要翻译：通常，一方面，一种方法包括形成具有N-扩散和P-扩散区域的半导体衬底。在半导体衬底上形成栅叠层。栅电极硬掩模形成在栅叠层上。栅极电极硬掩模用隔离材料增加在通过栅极晶体管周围。使用增强的栅极电极硬掩模蚀刻栅极堆叠以形成栅电极。通过栅极周围的栅电极具有比其它栅电极更大的长度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式