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1. 发明授权

US07138316B2 Semiconductor channel on insulator structure 有权
标题翻译：半导体通道绝缘体结构
公开(公告)号：US07138316B2
公开(公告)日：2006-11-21
申请号：US10669064
申请日：2003-09-23
申请人： Been-Yih Jin , Brian S. Doyle , Scott A. Hareland , Mark L. Doczy , Matthew V. Metz , Boyan I. Boyanov , Suman Datta , Jack T. Kavalieros , Robert S. Chau
发明人： Been-Yih Jin , Brian S. Doyle , Scott A. Hareland , Mark L. Doczy , Matthew V. Metz , Boyan I. Boyanov , Suman Datta , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02466 , H01L21/02532 , H01L21/02546 , H01L21/02549 , H01L21/02639 , H01L21/02647 , H01L21/02664 , H01L21/76877 , H01L21/76879 , H01L21/76886 , H01L29/66742 , H01L29/78603 , H01L29/78648 , H01L29/78681
摘要： A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.
摘要翻译：一种包括在半导体器件基板上形成通孔电介质层的方法; 在所述通孔电介质层上形成沟槽电介质层; 通过所述沟槽电介质层形成沟槽以暴露所述通孔电介质层; 在所述通孔电介质层中通过所述沟槽形成通孔以暴露所述衬底; 以及在通孔和沟槽中形成半导体材料。一种装置，包括：装置基板; 形成在所述器件基板的表面上的电介质层; 以及形成在所述电介质层上的器件基底，其包括衍生自所述器件基板的晶体结构。

2. 发明申请

US20110180851A1 CMOS DEVICES WITH A SINGLE WORK FUNCTION GATE ELECTRODE AND METHOD OF FABRICATION 有权
标题翻译：具有单个工作功能门电极的CMOS器件及其制造方法
公开(公告)号：US20110180851A1
公开(公告)日：2011-07-28
申请号：US13038190
申请日：2011-03-01
申请人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
发明人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
IPC分类号： H01L29/772
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1211 , H01L29/0673 , H01L29/068 , H01L29/1054 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.
摘要翻译：这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。

3. 发明授权

US08294180B2 CMOS devices with a single work function gate electrode and method of fabrication 有权
标题翻译： CMOS器件具有单功能功能的栅电极和制造方法
公开(公告)号：US08294180B2
公开(公告)日：2012-10-23
申请号：US13038190
申请日：2011-03-01
申请人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
发明人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
IPC分类号： H01L29/66
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1211 , H01L29/0673 , H01L29/068 , H01L29/1054 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.
摘要翻译：这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。

4. 发明授权

US07902014B2 CMOS devices with a single work function gate electrode and method of fabrication 有权
标题翻译： CMOS器件具有单功能功能的栅电极和制造方法
公开(公告)号：US07902014B2
公开(公告)日：2011-03-08
申请号：US11649545
申请日：2007-01-03
申请人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
发明人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
IPC分类号： H01L21/8234
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1211 , H01L29/0673 , H01L29/068 , H01L29/1054 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.
摘要翻译：这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。

5. 发明授权

US08169027B2 Substrate band gap engineered multi-gate pMOS devices 有权
标题翻译：基板带隙工程多栅极pMOS器件
公开(公告)号：US08169027B2
公开(公告)日：2012-05-01
申请号：US12757917
申请日：2010-04-09
申请人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta
发明人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta
IPC分类号： H01L29/66
CPC分类号： H01L29/78687 , H01L29/66545 , H01L29/785 , H01L29/78609
摘要： A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.
摘要翻译：多栅极晶体管和形成多栅极晶体管的方法，所述多栅极晶体管包括具有上部和下部的鳍。所述上部具有第一带隙，并且所述下部具有与所述第一带隙和所述第二带隙的第二带隙，所述第二带隙被设计成阻止电流从所述上部向下部流动。多栅极晶体管还包括具有与所述上部和所述下部电耦合的侧壁的栅极结构和位于鳍下方的衬底。

6. 发明申请

US20100193840A1 SUBSTRATE BAND GAP ENGINEERED MULTI-GATE PMOS DEVICES 有权
标题翻译：基板带隙工程多栅极PMOS器件
公开(公告)号：US20100193840A1
公开(公告)日：2010-08-05
申请号：US12757917
申请日：2010-04-09
申请人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta
发明人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta
IPC分类号： H01L27/088
CPC分类号： H01L29/78687 , H01L29/66545 , H01L29/785 , H01L29/78609
摘要： A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.
摘要翻译：多栅极晶体管和形成多栅极晶体管的方法，所述多栅极晶体管包括具有上部和下部的鳍。所述上部具有第一带隙，并且所述下部具有与所述第一带隙和所述第二带隙的第二带隙，所述第二带隙被设计成阻止电流从所述上部向下部流动。多栅极晶体管还包括具有与所述上部和所述下部电耦合的侧壁的栅极结构和位于鳍下方的衬底。

7. 发明授权

US07235809B2 Semiconductor channel on insulator structure 有权
标题翻译：半导体通道绝缘体结构
公开(公告)号：US07235809B2
公开(公告)日：2007-06-26
申请号：US11292911
申请日：2005-12-01
申请人： Been-Yih Jin , Brian S. Doyle , Scott A. Hareland , Mark L. Doczy , Matthew V. Metz , Boyan I. Boyanov , Suman Datta , Jack T. Kavalieros , Robert S. Chau
发明人： Been-Yih Jin , Brian S. Doyle , Scott A. Hareland , Mark L. Doczy , Matthew V. Metz , Boyan I. Boyanov , Suman Datta , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L29/06
CPC分类号： H01L29/66772 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02466 , H01L21/02532 , H01L21/02546 , H01L21/02549 , H01L21/02639 , H01L21/02647 , H01L21/02664 , H01L21/76877 , H01L21/76879 , H01L21/76886 , H01L29/66742 , H01L29/78603 , H01L29/78648 , H01L29/78681
摘要： A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.
摘要翻译：一种包括在半导体器件基板上形成通孔电介质层的方法; 在所述通孔电介质层上形成沟槽电介质层; 通过所述沟槽电介质层形成沟槽以暴露所述通孔电介质层; 在所述通孔电介质层中通过所述沟槽形成通孔以暴露所述衬底; 以及在通孔和沟槽中形成半导体材料。一种装置，包括：装置基板; 形成在所述器件基板的表面上的电介质层; 以及形成在所述电介质层上的器件基底，其包括衍生自所述器件基板的晶体结构。

8. 发明授权

US07767560B2 Three dimensional strained quantum wells and three dimensional strained surface channels by Ge confinement method 有权
标题翻译：三维应变量子阱和三维应变表面通道的Ge约束法
公开(公告)号：US07767560B2
公开(公告)日：2010-08-03
申请号：US11864963
申请日：2007-09-29
申请人： Been-Yih Jin , Robert S. Chau , Brian S. Doyle , Jack T. Kavalieros
发明人： Been-Yih Jin , Robert S. Chau , Brian S. Doyle , Jack T. Kavalieros
IPC分类号： H01L21/36 , H01L21/20
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02664 , H01L29/0673 , H01L29/1054 , H01L29/66818 , H01L29/7851
摘要： The present disclosure describes a method and apparatus for implementing a 3D (three dimensional) strained high mobility quantum well structure, and a 3D strained surface channel structure through a Ge confinement method. One exemplary apparatus may include a first graded SiGe fin on a Si substrate. The first graded SiGe fin may have a maximum Ge concentration greater than about 60%. A Ge quantum well may be on the first graded SiGe fin and a SiGe quantum well upper barrier layer may be on the Ge quantum well. The exemplary apparatus may further include a second graded SiGe fin on the Si substrate. The second graded SiGe fin may have a maximum Ge concentration less than about 40%. A Si active channel layer may be on the second graded SiGe fin. Other high mobility materials such as III-V semiconductors may be used as the active channel materials. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开描述了通过Ge约束法实现3D（三维）应变高迁移量子阱结构和3D应变表面通道结构的方法和装置。一个示例性设备可以包括在Si衬底上的第一梯度SiGe鳍。第一级的SiGe鳍可以具有大于约60％的最大Ge浓度。 Ge量子阱可以在第一等级的SiGe鳍上，SiGe量子阱上阻挡层可以在Ge量子阱上。示例性设备还可以包括在Si衬底上的第二渐变SiGe鳍。第二级的SiGe鳍可以具有小于约40％的最大Ge浓度。 Si活性沟道层可以在第二级别的SiGe鳍上。可以使用诸如III-V族半导体的其它高迁移率材料作为活性通道材料。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

9. 发明授权

US07745270B2 Tri-gate patterning using dual layer gate stack 有权
标题翻译：使用双层栅极堆叠的三栅极图案化
公开(公告)号：US07745270B2
公开(公告)日：2010-06-29
申请号：US12006047
申请日：2007-12-28
申请人： Uday Shah , Brian S. Doyle , Jack T. Kavalieros , Been-Yih Jin
发明人： Uday Shah , Brian S. Doyle , Jack T. Kavalieros , Been-Yih Jin
IPC分类号： H01L21/84
CPC分类号： H01L21/823821 , H01L29/66795 , H01L29/785
摘要： In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is formed over the substrate. A first work function metal layer is created over the n-diffusion fin and a second work function metal layer, thicker than the first, is created over the n-diffusion fin. A silicon germanium layer is formed over the first and second work function metal layers. A polysilicon layer is formed over the silicon germanium layer and is polished. The polysilicon layer over the first work function metal layer is thicker than the polysilicon layer over the second work function metal layer. A hard mask is patterned and used to etch the polysilicon layer and the silicon germanium layer to create gate stacks. The etch rate of the silicon germanium layer is faster over the first work function metal layer.
摘要翻译：通常，在一个方面，一种方法包括在半导体衬底中形成n扩散鳍和p扩散鳍。在衬底上形成高介电常数层。在n扩散翅片上形成第一功函数金属层，并在n扩散鳍片上形成比第一功函数金属层厚的第二功函数金属层。在第一和第二功函数金属层上形成硅锗层。在硅锗层上形成多晶硅层并进行抛光。第一功函数金属层上的多晶硅层比第二功函数金属层上的多晶硅层厚。硬掩模被图案化并用于蚀刻多晶硅层和硅锗层以产生栅极堆叠。硅锗层的蚀刻速率比第一功函数金属层更快。

10. 发明申请

US20070287255A1 Protection of three dimensional transistor structures during gate stack etch 有权
标题翻译：在栅堆叠蚀刻期间保护三维晶体管结构
公开(公告)号：US20070287255A1
公开(公告)日：2007-12-13
申请号：US11452883
申请日：2006-06-13
申请人： Brian S. Doyle , Uday Shah , Been-Yih Jin , Jack T. Kavalieros
发明人： Brian S. Doyle , Uday Shah , Been-Yih Jin , Jack T. Kavalieros
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： Embodiments of the invention include apparatuses and methods relating to three dimensional transistors having high-k dielectrics and metal gates with fins protected by a hard mask layer on their top surface. In one embodiment, the hard mask layer includes an oxide.
摘要翻译：本发明的实施例包括与具有高k电介质的三维晶体管和金属栅极相关的装置和方法，其翅片由其顶表面上的硬掩模层保护。在一个实施例中，硬掩模层包括氧化物。

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