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1. 发明授权

US4723242A Digital adaptive voting 失效
标题翻译：数字自适应投票
公开(公告)号：US4723242A
公开(公告)日：1988-02-02
申请号：US879695
申请日：1986-06-27
申请人： Brian R. Larson , Donald B. Bennett , Thomas O. Wolff
发明人： Brian R. Larson , Donald B. Bennett , Thomas O. Wolff
IPC分类号： G06F11/18
CPC分类号： G06F11/187 , G06F11/183
摘要： A digital system employing adaptive voting circuitry to improve its fault-tolerance receives an input data bit from each of a number of input data sources. The adaptive voting circuitry has a separate section for each of the input devices which has a weight register that stores an initial weight value which determines the voting strength of the associated input device. The weight values are multiplexed through to a voting circuit which also receives the input data bits. If an input data bit is a logic "1" the weight value of the input data device that supplied this "1" signal is added to the weight values of all other input data devices that supplied "1" data bits. If the data bit from a particular input device is a logic "0", then its weight is added to the weight values for other input data devices which supplied logic "0'". Accumulative voting then takes place via adders in the voting circuit which determines whether the correct output bit should be a logic "1" or a logic "0". After the correct output bit is obtained, it is compared with the input bits supplied by the different input data devices, and the stoned weight values associated with each of these are decremented if the input device supplied a data bit that did not conform to the correct output bit, or alternately they are incremented if it did.
摘要翻译：采用自适应投票电路来提高其容错能力的数字系统从多个输入数据源中的每一个接收输入数据位。自适应投票电路具有用于每个输入设备的单独部分，其具有存储初始权重值的权重寄存器，该初始权重值确定相关联的输入设备的投票强度。重量值被复用到也接收输入数据位的投票电路。如果输入数据位为逻辑“1”，则提供该“1”信号的输入数据装置的权重值被加到提供“1”数据位的所有其它输入数据装置的权重值中。如果来自特定输入设备的数据位为逻辑“0”，则将其权重加到提供逻辑“0”的其他输入数据设备的权重值中。然后累积投票通过投票电路中的加法器进行，确定正确的输出位是逻辑“1”还是逻辑“0”。在获得正确的输出位之后，将其与由不同输入数据设备提供的输入位进行比较，并且如果输入设备提供的数据位不符合正确的数据位，则与每个输入数据相关联的stoned权重值递减输出位，或者交替地，如果它们是递增的。

2. 发明授权

US4833468A Layered network 失效
标题翻译：分层网络
公开(公告)号：US4833468A
公开(公告)日：1989-05-23
申请号：US108514
申请日：1987-10-14
申请人： Brian R. Larson , Donald B. Bennett , Steven A. Murphy
发明人： Brian R. Larson , Donald B. Bennett , Steven A. Murphy
IPC分类号： G06F15/16 , G06F13/00 , G06F15/173 , H04L12/56 , H04Q3/52 , H04Q3/68
CPC分类号： H04Q3/68 , G06F15/17337 , H04L49/1507 , H04L49/101 , H04L49/205 , H04L49/254 , H04L49/40
摘要： A Layered Network system may provide varying cost from order NlogN low-cost networds, to completely-routing, fully-Layered networks with cots of order Nlog .sup.3 N. Layered networks are composed of switches and point-to-point connections between them. These networks establish connections from requestors to responders by relaying "requests" through the switches. Each switch has built-in control logic to route requests and responses. The switch setting is determined using the comparison of the request with the request's current location in the network, and with locally competing requests. To provide distributed routing without a centralized controller, each switch routes the requests using only the information contained in the requests that switch handles. The switch setting is remembered in order to route the responses on the same paths as the associated requests, but in the reverse direction.
摘要翻译：分层网络系统可以提供从NlogN订单低成本网络到完全路由的完全分层网络，具有Nlog 3N订单的成本。分层网络由交换机和它们之间的点对点连接组成。这些网络通过交换机中继“请求”来建立从请求者到响应者的连接。每个交换机都有内置的控制逻辑来路由请求和响应。交换机设置是使用请求与请求在网络中当前位置的比较以及本地竞争的请求来确定的。为了提供没有集中控制器的分布式路由，每个交换机只使用交换机处理的请求中包含的信息来路由请求。记住切换设置，以便在与相关请求相同的路径上路由响应，但是反向。

3. 发明授权

US4498177A M Out of N code checker circuit 失效
标题翻译： M出N码检查电路
公开(公告)号：US4498177A
公开(公告)日：1985-02-05
申请号：US412487
申请日：1982-08-30
申请人： Brian R. Larson
发明人： Brian R. Larson
IPC分类号： G06F11/08 , H03M7/20 , H03M13/51 , H03K13/32
CPC分类号： G06F11/085 , H03M13/51 , H03M7/20
摘要： An N bit input word is partitioned into parts, preferably N/3 parts of 3 bits each. Each part is counted in parallel for the number of binary ones contained therein in first stage parallel code generators, preferably in N/3 parallel berger code generators each producing on 2 binary encoded signal lines that number of binary ones as are contained within 3 input signal lines. The binary encoded signal lines from the parallel code generators are added in a second stage binary tree of adders, such adders as are used in conjunction with first stage berger code generators progressing from N/6 adders of 2 bits width at level 1 to 1 adder of ln.sub.2 (N/3)+1 bits width at level ln.sub.2 (N/3). The final adder produces (X+1) binary encoded signals representing the number of binary ones contained within the input word, 2.sup.X+1.gtoreq. N. A final comparator stage based on exclusive OR gates and an OR gate(s) compares the X+1 signals representing the actual bit count with an equal number of binary encoded signals representing the then desired number M, M.ltoreq.N, and produces an error signal if the number of binary ones detected is not equal to M. A preferred embodiment implementation of the berger code generator circuits utilizes exclusive OR logical elements based on the CMOS technology transfer gate structure.
摘要翻译：一个N位输入字被分成多个部分，最好是每个3位的N / 3部分。对于第一级并行码发生器中包含的二进制数的数量，每个部分被并行计数，优选地在N / 3个并行发生器代码发生器中，每个二进制编码信号线产生包含在3个输入信号内的二进制编码信号线线条。来自并行代码生成器的二进制编码信号线被添加在加法器的第二级二进制树中，这些加法器与从第1级的2位宽度的N / 6加法器到1加法器的第一级合并代码生成器一起使用 ln2（N / 3）+1位宽度，级别ln2（N / 3）。最终加法器产生（X + 1）二进制编码信号，表示输入字2X + 1> / = N中包含的二进制数。基于异或门和或门的最终比较器级将表示实际位计数的X + 1信号与表示当时期望数M M N的相等数量的二进制编码信号进行比较，并产生如果检测到的二进制数的数目不等于M，则误差信号。该合并代码生成器电路的优选实施方式基于CMOS技术传输门结构使用异或逻辑元件。

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