专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06766381B1 VLSI network processor and methods 失效
标题翻译： VLSI网络处理器和方法
公开(公告)号：US06766381B1
公开(公告)日：2004-07-20
申请号：US09384689
申请日：1999-08-27
申请人： Kenneth James Barker , Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
发明人： Kenneth James Barker , Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
IPC分类号： G06F1516
CPC分类号： H04L29/06 , H04L49/1507 , H04L49/45 , H04L69/12
摘要： A network processor useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of a plurality of interface processors formed on a semiconductor substrate. The interface processors provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate.
摘要翻译：可用于网络交换设备的网络处理器和操作这样的处理器的方法，其中通过形成在半导体衬底上的多个接口处理器的协作来增强数据流处理和灵活性。接口处理器提供用于入站和出站数据流的数据路径，并且在存储在形成在半导体衬底上的指令存储器中的指令的控制下操作。

2. 发明授权

US06557053B1 Queue manager for a buffer 失效
标题翻译：队列管理器为缓冲区
公开(公告)号：US06557053B1
公开(公告)日：2003-04-29
申请号：US09477179
申请日：2000-01-04
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
IPC分类号： G06F1314
CPC分类号： G06F13/1673
摘要： A bandwidth conserving queue manager for a FIFO buffer is provided, preferably on an ASIC chip and preferably including separate DRAM storage that maintains a FIFO queue which can extend beyond the data storage space of the FIFO buffer to provide additional data storage space as needed. FIFO buffers are used on the ASIC chip to store and retrieve multiple queue entries. As long as the total size of the queue does not exceed the storage available in the buffers, no additional data storage is needed. However, when some predetermined amount of the buffer storage space in the FIFO buffers is exceeded, data are written to and read from the additional data storage, and preferably in packets which are of optimum size for maintaining peak performance of the data storage device and which are written to the data storage device in such a way that they are queued in a first-in, first-out (FIFO) sequence of addresses. Preferably, the data are written to and are read from the DRAM in burst mode.
摘要翻译：提供了用于FIFO缓冲器的带宽保存队列管理器，优选地在ASIC芯片上，并且优选地包括分离的DRAM存储器，其维持FIFO队列，其可以超出FIFO缓冲器的数据存储空间，以根据需要提供附加的数据存储空间。在ASIC芯片上使用FIFO缓冲器来存储和检索多个队列条目。只要队列的总大小不超过缓冲区中可用的存储空间，则不需要额外的数据存储。然而，当超过FIFO缓冲器中的一些预定量的缓冲存储空间时，数据被写入附加数据存储器并从其中读出，并且优选地是具有用于保持数据存储设备的峰值性能的最佳尺寸的数据包，以及哪个被写入数据存储设备，使得它们以先入先出（FIFO）地址序列排队。优选地，以突发模式将数据写入DRAM并从DRAM读取。

3. 发明授权

US06584518B1 Cycle saving technique for managing linked lists 失效
标题翻译：用于管理链表的循环保存技术
公开(公告)号：US06584518B1
公开(公告)日：2003-06-24
申请号：US09479751
申请日：2000-01-07
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
IPC分类号： G06F1314
CPC分类号： G06F12/023
摘要： A method and system for queueing data within a data storage device including a set of storage blocks each having an address, a pointer field, and a data field. This set of storage blocks comprises a linked list of associated storage blocks and also a free pool of available storage blocks. The storage device further includes a tail register for tracking an empty tail block from which a data object is enqueued into the linked list. A request to enqueue a data object into the linked list is received within the data storage system. In response to the data enqueue request, an available storage block from the free pool is selected and associated with the tail register. A single write operation is then required to write the data object into the data field of a current tail block and to write the address of the selected storage block into the pointer field of the current tail block, such that the selected storage block becomes a new tail block to which the tail register points.
摘要翻译：一种用于在数据存储设备内排队数据的方法和系统，包括一组存储块，每个存储块具有地址，指针字段和数据字段。这组存储块包括相关联的存储块的链表以及可用存储块的空闲池。存储装置还包括用于跟踪空尾部块的尾部寄存器，数据对象从该尾部块排入链接列表。在数据存储系统内接收到将数据对象排入链表的请求。响应于数据排入请求，从空闲池中选择一个可用的存储块并将其与尾部寄存器相关联。然后需要单个写入操作来将数据对象写入当前尾部块的数据字段，并将所选择的存储块的地址写入当前尾部块的指针字段，使得所选择的存储块变为新的尾部寄存器指向的尾部块。

4. 发明授权

US06473838B1 Data transfer system for multiple network processors using dual DRAM storage 失效
标题翻译：使用双DRAM存储的多个网络处理器的数据传输系统
公开(公告)号：US06473838B1
公开(公告)日：2002-10-29
申请号：US09477576
申请日：2000-01-04
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Steven Kenneth Jenkins , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Steven Kenneth Jenkins , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
IPC分类号： G06F1200
CPC分类号： G06F13/1647 , G06F15/167
摘要： The ability of network processors to move data to and from dynamic random access memory (DRAM) chips used in computer systems is enhanced in several respects. In one aspect of the invention, two double data rate DRAMS are used in parallel to double the bandwidth for increased throughput of data. The movement of data is further improved by setting 4 banks of full ‘read’ and 4 banks of full ‘write’ by the network processor for every repetition of the DRAM time clock. A scheme for randomized ‘read’ and ‘write’ access by the network processor is disclosed. This scheme is particularly applicable to networks such as Ethernet that utilize variable frame sizes.
摘要翻译：网络处理器在计算机系统中使用的动态随机存取存储器（DRAM）芯片中移动数据的能力在几个方面得到了增强。在本发明的一个方面，并行使用两个双数据速率DRAMS以使带宽增加一倍以增加数据吞吐量。数据的移动通过为DRAM时钟的每次重复通过网络处理器设置4组完整“读”和4组完整“写”来进一步改进。公开了一种由网络处理器进行随机“读取”和“写入”访问的方案。该方案特别适用于利用可变帧大小的诸如以太网的网络。

5. 发明申请

US20080098176A1 Method and Apparatus for Implementing Memory Accesses Using Open Page Mode for Data Prefetching 审中-公开
标题翻译：使用开放页面模式实现存储器访问的方法和装置用于数据预取
公开(公告)号：US20080098176A1
公开(公告)日：2008-04-24
申请号：US11550468
申请日：2006-10-18
申请人： M. V. V. Anil Krishna , Michael Raymond Trombley , Steven Paul VanderWeil
发明人： M. V. V. Anil Krishna , Michael Raymond Trombley , Steven Paul VanderWeil
IPC分类号： G06F12/00
CPC分类号： G06F12/0215 , G06F13/1631
摘要： A method and apparatus implement memory accesses to a memory using an open page mode with data prefetching. A central processor unit issues memory commands. A memory controller receiving the memory commands, identifies a data prefetching command. The memory controller checks whether a next sequential line for the identified prefetch command is within the page currently being accessed, and responsive to identifying the next sequential line being within the current page, the current command is processed and the current page left open.
摘要翻译：一种使用具有数据预取的开放页面模式对存储器进行存储器访问的方法和装置。中央处理器单元发出存储器命令。接收存储器命令的存储器控制器识别数据预取命令。存储器控制器检查所识别的预取命令的下一个顺序行是否在当前被访问的页内，并且响应于识别当前页面中的下一个顺序行，处理当前命令并且当前页面打开。

6. 发明申请

US20080059728A1 Systems and methods for masking latency of memory reorganization work in a compressed memory system 失效
标题翻译：用于屏蔽存储器重组延迟的系统和方法在压缩存储器系统中工作
公开(公告)号：US20080059728A1
公开(公告)日：2008-03-06
申请号：US11516207
申请日：2006-09-06
申请人： David Michael Daly , Peter Anthony Franaszek , Michael Ignatowski , Luis Alfonso Lastras-Montano , Michael Raymond Trombley
发明人： David Michael Daly , Peter Anthony Franaszek , Michael Ignatowski , Luis Alfonso Lastras-Montano , Michael Raymond Trombley
IPC分类号： G06F13/28
CPC分类号： G06F12/08 , G06F12/0804 , G06F12/1408 , G06F2212/401
摘要： Computer memory management systems and methods are provided in which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory. In particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory reorganization work to allow resources to be used for serving new memory access requests and other high priority commands.
摘要翻译：提供了计算机存储器管理系统和方法，其中在压缩存储器系统中利用数据块缓冲和优先级调度协议来掩盖在访问压缩主存储器之后与存储器重组工作相关联的等待时间。特别地，实现数据块缓冲器和优先级调度协议以延迟和优先化存储器重组工作，以允许资源用于服务新的存储器访问请求和其他高优先级命令。

7. 发明授权

US07949830B2 System and method for handling data requests 失效
标题翻译：用于处理数据请求的系统和方法
公开(公告)号：US07949830B2
公开(公告)日：2011-05-24
申请号：US11953255
申请日：2007-12-10
申请人： James Johnson Allen, Jr. , Steven Kenneth Jenkins , James A. Mossman , Michael Raymond Trombley
发明人： James Johnson Allen, Jr. , Steven Kenneth Jenkins , James A. Mossman , Michael Raymond Trombley
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0806 , G06F2212/507
摘要： A system and method for handling speculative read requests for a memory controller in a computer system are provided. In one example, a method includes the steps of providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and intermixing demand reads and speculative reads in accordance with the speculative read threshold. In another example, a computer system includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold. In another example, a method includes the steps of providing a speculative dispatch time threshold corresponding to a selected percentage of a period of time required to search a cache of the computer system, and intermixing demand reads and speculative reads in accordance with the speculative dispatch time threshold.
摘要翻译：提供了一种用于处理计算机系统中的存储器控制器的推测读请求的系统和方法。在一个示例中，一种方法包括以下步骤：提供与可推测性地发布的总读数的选定百分比相对应的推测读取阈值，以及根据推测读取阈值混合需求读取和推测性读取。在另一示例中，计算机系统包括CPU，存储器控制器，存储器，连接CPU，存储器控制器和存储器的总线，用于提供对应于可以推测地读取总数的所选百分比的推测读取阈值的电路以及根据推测性读取阈值来混合需求读取和推测性读取的电路。在另一示例中，一种方法包括以下步骤：提供与搜索计算机系统的高速缓存所需的时间段的选定百分比相对应的推测性调度时间阈值，以及根据投机调度时间混合需求读取和推测读取阈。

8. 发明申请

US20090150401A1 SYSTEM AND METHOD FOR HANDLING DATA ACCESS 有权
标题翻译：用于处理数据访问的系统和方法
公开(公告)号：US20090150401A1
公开(公告)日：2009-06-11
申请号：US11953201
申请日：2007-12-10
申请人： James Johnson Allen, JR. , Steven Kenneth Jenkins , James A. Mossman , Michael Raymond Trombley
发明人： James Johnson Allen, JR. , Steven Kenneth Jenkins , James A. Mossman , Michael Raymond Trombley
IPC分类号： G06F17/30 , G06F12/00
CPC分类号： G06F12/0862
摘要： A method for handling speculative access requests for a storage device in a computer system is provided. The method includes the steps of providing a speculative access threshold corresponding to a selected percentage of the total number of accesses to be speculatively issued, and intermixing demand accesses and speculative accesses in accordance with the speculative access threshold. In another embodiment, a method for reducing data access latency experienced by a user in a computer network is provided. The method includes the steps of providing a web page comprising a link to a data file stored on a database connected to the computer network, selecting a speculative access threshold corresponding to a selected percentage of data accesses which are to be speculatively provided to the user, and speculatively providing the data file in accordance with the speculative access threshold.
摘要翻译：提供了一种用于处理计算机系统中的存储设备的推测访问请求的方法。该方法包括以下步骤：提供与被推测发布的总访问次数的选定百分比相对应的推测访问阈值，以及根据推测访问阈值混合请求访问和推测访问。在另一个实施例中，提供了一种用于减少用户在计算机网络中经历的数据访问延迟的方法。该方法包括以下步骤：提供网页，其包括链接到存储在连接到计算机网络的数据库上的数据文件的链接，选择与要推测性地提供给用户的所选百分比的数据访问相对应的推测访问阈值，并根据推测访问阈值推测提供数据文件。

9. 发明申请

US20090150622A1 SYSTEM AND METHOD FOR HANDLING DATA REQUESTS 失效
标题翻译：用于处理数据请求的系统和方法
公开(公告)号：US20090150622A1
公开(公告)日：2009-06-11
申请号：US11953255
申请日：2007-12-10
申请人： James Johnson Allen, JR. , Steven Kenneth Jenkins , James A. Mossman , Michael Raymond Trombley
发明人： James Johnson Allen, JR. , Steven Kenneth Jenkins , James A. Mossman , Michael Raymond Trombley
IPC分类号： G06F12/00
CPC分类号： G06F12/0806 , G06F2212/507
摘要： A system and method for handling speculative read requests for a memory controller in a computer system are provided. In one example, a method includes the steps of providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and intermixing demand reads and speculative reads in accordance with the speculative read threshold. In another example, a computer system includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold. In another example, a method includes the steps of providing a speculative dispatch time threshold corresponding to a selected percentage of a period of time required to search a cache of the computer system, and intermixing demand reads and speculative reads in accordance with the speculative dispatch time threshold.
摘要翻译：提供了一种用于处理计算机系统中的存储器控制器的推测读请求的系统和方法。在一个示例中，一种方法包括以下步骤：提供与可推测性地发布的总读数的选定百分比相对应的推测读取阈值，以及根据推测读取阈值混合需求读取和推测性读取。在另一示例中，计算机系统包括CPU，存储器控制器，存储器，连接CPU，存储器控制器和存储器的总线，用于提供对应于可以推测地读取总数的所选百分比的推测读取阈值的电路以及根据推测性读取阈值来混合需求读取和推测性读取的电路。在另一示例中，一种方法包括以下步骤：提供与搜索计算机系统的高速缓存所需的时间段的选定百分比相对应的推测性调度时间阈值，以及根据投机调度时间混合需求读取和推测读取阈。

10. 发明授权

US06601229B1 Client/server behavioral modeling and testcase development using VHDL for improved logic verification 失效
标题翻译：使用VHDL进行客户端/服务器行为建模和测试用例开发，以改进逻辑验证
公开(公告)号：US06601229B1
公开(公告)日：2003-07-29
申请号：US09521990
申请日：2000-03-09
申请人： Theron Paul Niederer , Raj Kumar Singh , Michael Raymond Trombley
发明人： Theron Paul Niederer , Raj Kumar Singh , Michael Raymond Trombley
IPC分类号： G06F1750
CPC分类号： G01R31/318357 , G01R31/318364 , G06F17/5022
摘要： A system, method and computer program features of the present invention, relate to verification or simulation of a design using a behavioral model structure for use in a Client/Server configuration. A physical part presents the external interface, and a functional procedural part which is comprised of at least one VHDL process. A testcase is a set of procedure calls written in VHDL. The present invention describes the architecture and implementation of a client/server behavioral model and procedural approach for testcase development which results in significant gain in productivity, quality of logic verification, and portability.
摘要翻译：本发明的系统，方法和计算机程序特征涉及使用用于客户端/服务器配置的行为模型结构的设计的验证或模拟。物理部分呈现外部接口，以及由至少一个VHDL进程组成的功能性程序部分。测试用例是用VHDL编写的一组过程调用。本发明描述了用于测试用例开发的客户机/服务器行为模型和程序方法的架构和实现，其导致生产率的显着增加，逻辑验证的质量和可移植性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式