专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080130667A1 DISTRIBUTED ARBITRATION MECHANISM FOR RING NETWORKS 审中-公开
标题翻译：用于环网的分布式仲裁机制
公开(公告)号：US20080130667A1
公开(公告)日：2008-06-05
申请号：US11564863
申请日：2006-11-30
申请人： Brian M. Bass , Timothy H. Heil , Michael S. Siegel , Jeffrey R. Summers , Tiffany Tamaddoni-Jahromi , Steven P. VanderWiel
发明人： Brian M. Bass , Timothy H. Heil , Michael S. Siegel , Jeffrey R. Summers , Tiffany Tamaddoni-Jahromi , Steven P. VanderWiel
IPC分类号： H04L12/66
CPC分类号： H04L12/66
摘要： A system for employing a scalable distributed arbitration scheme, including: a plurality of stations interconnected via a ring topology for transferring data between the plurality of stations; and a bus coupling the plurality of stations in the ring topology; wherein each of the plurality of stations on the topology ring is permitted to independently make a decision when to load their data on the topology ring by evaluating a set of inputs.
摘要翻译：一种采用可扩展分布仲裁方案的系统，包括：通过环形拓扑互连的多个站，用于在多个站之间传送数据; 以及耦合所述环形拓扑中的所述多个站的总线; 其中允许拓扑环上的多个站中的每一个通过评估一组输入来独立地决定何时将其数据加载到拓扑环上。

2. 发明授权

US07944931B2 Balanced bandwidth utilization 失效
标题翻译：平衡带宽利用率
公开(公告)号：US07944931B2
公开(公告)日：2011-05-17
申请号：US11776162
申请日：2007-07-11
申请人： Brian M. Bass , Gordon T. Davis , Michael S. Siegel , Michael R. Trombley
发明人： Brian M. Bass , Gordon T. Davis , Michael S. Siegel , Michael R. Trombley
IPC分类号： H04L12/28 , H04J3/24
CPC分类号： H04L49/9042 , H04L49/90 , H04L2012/5681
摘要： A memory subsystem includes Data Store 0 and Data Store 1. Each data store is partitioned into N buffers, N>1. An increment of memory is formed by a buffer pair, with each buffer of the buffer pair being in a different data store. Two buffer pair formats are used in forming memory increments. A first format selects a first buffer from Data Store 0 and a second buffer from Data Store 1, while a second format selects a first buffer from Data Store 1 and a second buffer from Data Store 0. A controller selects a buffer pair for storing data based upon the configuration of data in a delivery mechanism, such as switch cell.
摘要翻译：存储器子系统包括数据存储0和数据存储1.每个数据存储分区为N个缓冲区，N> 1。存储器的增量由缓冲器对形成，缓冲器对的每个缓冲器在不同的数据存储器中。两个缓冲器对格式用于形成存储器增量。第一格式从Data Store 0中选择第一个缓冲区，从Data Store 1中选择第二个缓冲区，而第二个格式从Data Store 1中选择第一个缓冲区，并从Data Store 0中选择一个第二个缓冲区。控制器选择一个用于存储数据的缓冲区基于诸如交换单元之类的递送机制中的数据的配置。

3. 发明申请

US20080240110A1 MEMORY SYSTEM WITH APPARATUS AND METHOD TO ENABLE BALANCED BANDWIDTH UTILIZATION 失效
标题翻译：具有装置的存储系统和使用平衡带宽利用的方法
公开(公告)号：US20080240110A1
公开(公告)日：2008-10-02
申请号：US11776162
申请日：2007-07-11
申请人： Brian M. Bass , Gordon T. Davis , Michael S. Siegel , Michael R. Trombley
发明人： Brian M. Bass , Gordon T. Davis , Michael S. Siegel , Michael R. Trombley
IPC分类号： H04L12/56
CPC分类号： H04L49/9042 , H04L49/90 , H04L2012/5681
摘要： A memory subsystem includes Data Store 0 and Data Store 1. Each data store is partitioned into N buffers, N>1. An increment of memory is formed by a buffer pair, with each buffer of the buffer pair being in a different data store. Two buffer pair formats are used in forming memory increments. A first format selects a first buffer from Data Store 0 and a second buffer from Data Store 1, while a second format selects a first buffer from Data Store 1 and a second buffer from Data Store 0. A controller selects a buffer pair for storing data based upon the configuration of data in a delivery mechanism, such as switch cell.
摘要翻译：内存子系统包括数据存储0和数据存储1。每个数据存储区分为N个缓冲区，N> 1。存储器的增量由缓冲器对形成，缓冲器对的每个缓冲器在不同的数据存储器中。两个缓冲器对格式用于形成存储器增量。第一种格式从Data Store 0中选择第一个缓冲区，从Data Store 1中选择第二个缓冲区，而第二种格式从Data Store 1中选择第一个缓冲区，从Data Store 0中选择第二个缓冲区。控制器基于诸如交换单元之类的传送机制中的数据的配置来选择用于存储数据的缓冲器对。

4. 发明授权

US07286543B2 Memory system with apparatus and method to enable balanced bandwidth utilization 失效
标题翻译：具有使平衡带宽利用的装置和方法的存储器系统
公开(公告)号：US07286543B2
公开(公告)日：2007-10-23
申请号：US10370550
申请日：2003-02-20
申请人： Brian M. Bass , Gordon T. Davis , Michael S. Siegel , Michael R. Trombley
发明人： Brian M. Bass , Gordon T. Davis , Michael S. Siegel , Michael R. Trombley
IPC分类号： H04L12/28 , H04J3/24
CPC分类号： H04L49/9042 , H04L49/90 , H04L2012/5681
摘要： A memory subsystem includes Data Store 0 and Data Store 1. Each data store is partitioned into N buffers, N>1. An increment of memory is formed by a buffer pair, with each buffer of the buffer pair being in a different data store. Two buffer pair formats are used in forming memory increments. A first format selects a first buffer from Data Store 0 and a second buffer from Data Store 1, while a second format selects a first buffer from Data Store 1 and a second buffer from Data Store 0. A controller selects a buffer pair for storing data based upon the configuration of data in a delivery mechanism, such as switch cell.
摘要翻译：存储器子系统包括数据存储0和数据存储1.每个数据存储分区为N个缓冲区，N> 1。存储器的增量由缓冲器对形成，缓冲器对的每个缓冲器在不同的数据存储器中。两个缓冲器对格式用于形成存储器增量。第一格式从Data Store 0中选择第一个缓冲区，从Data Store 1中选择第二个缓冲区，而第二个格式从Data Store 1中选择第一个缓冲区，并从Data Store 0中选择一个第二个缓冲区。控制器选择一个用于存储数据的缓冲区基于诸如交换单元之类的递送机制中的数据的配置。

5. 发明授权

US08489819B2 Victim cache lateral castout targeting 失效
标题翻译：受害者缓存横向倾斜定位
公开(公告)号：US08489819B2
公开(公告)日：2013-07-16
申请号：US12340511
申请日：2008-12-19
申请人： Guy L. Guthrie , Michael S. Siegel , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Michael S. Siegel , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/126 , G06F12/0811 , G06F12/0862
摘要： A data processing system includes a plurality of processing units coupled by an interconnect fabric. In response to a data request, a victim cache line is selected for castout from a first lower level cache of a first processing unit, and a target lower level cache of one of the plurality of processing units is selected based upon architectural proximity of the target lower level cache to a home system memory to which the address of the victim cache line is assigned. The first processing unit issues on the interconnect fabric a lateral castout (LCO) command that identifies the victim cache line to be castout from the first lower level cache and indicates that the target lower level cache is an intended destination. In response to a coherence response indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.
摘要翻译：数据处理系统包括通过互连结构耦合的多个处理单元。响应于数据请求，从第一处理单元的第一较低级别高速缓存中选择牺牲缓存行来进行舍弃，并且基于目标的体系结构接近来选择多个处理单元之一的目标下级高速缓存低级缓存到分配了受害者缓存行的地址的归属系统存储器。所述第一处理单元在所述互连结构上发出侧向锁定（LCO）命令，所述侧向锁定（LCO）命令标识要从所述第一低级缓存中抛出的所述牺牲缓存线，并且指示所述目标低级缓存是预期目的地。响应于指示LCO命令的成功的一致性响应，从第一低级缓存中删除受害者高速缓存行并保存在第二较低级高速缓存中。

6. 发明申请

US20120203976A1 MEMORY COHERENCE DIRECTORY SUPPORTING REMOTELY SOURCED REQUESTS OF NODAL SCOPE 失效
标题翻译：记忆协调指导原则支持远程请求的NODAL范围
公开(公告)号：US20120203976A1
公开(公告)日：2012-08-09
申请号：US13445010
申请日：2012-04-12
申请人： Paul A. Ganfield , Guy L. Guthrie , David J. Krolak , Michael S. Siegel , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
发明人： Paul A. Ganfield , Guy L. Guthrie , David J. Krolak , Michael S. Siegel , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0817
摘要： A data processing system includes at least a first through third processing nodes coupled by an interconnect fabric. The first processing node includes a master, a plurality of snoopers capable of participating in interconnect operations, and a node interface that receives a request of the master and transmits the request of the master to the second processing unit with a nodal scope of transmission limited to the second processing node. The second processing node includes a node interface having a directory. The node interface of the second processing node permits the request to proceed with the nodal scope of transmission if the directory does not indicate that a target memory block of the request is cached other than in the second processing node and prevents the request from succeeding if the directory indicates that the target memory block of the request is cached other than in the second processing node.
摘要翻译：数据处理系统至少包括通过互连结构耦合的第一至第三处理节点。第一处理节点包括主机，能够参与互连操作的多个侦听器，以及接收主机请求的节点接口，并将主机的请求传送到第二处理单元，传送范围限于第二处理节点。第二处理节点包括具有目录的节点接口。第二处理节点的节点接口允许请求继续进行节点传输范围，如果该目录没有指示该请求的目标存储器块不是在第二处理节点中被缓存，并且如果该请求成功目录指示除第二处理节点之外的请求的目标存储块被缓存。

7. 发明申请

US20100235576A1 Handling Castout Cache Lines In A Victim Cache 失效
标题翻译：在受害者缓存中处理Castout缓存行
公开(公告)号：US20100235576A1
公开(公告)日：2010-09-16
申请号：US12336048
申请日：2008-12-16
申请人： Guy L. Guthrie , Alvan W. Ng , Michael S. Siegel , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： Guy L. Guthrie , Alvan W. Ng , Michael S. Siegel , William J. Starke , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/127 , G06F12/0811 , G06F12/0862
摘要： A victim cache memory includes a cache array, a cache directory of contents of the cache array, and a cache controller that controls operation of the victim cache memory. The cache controller, responsive to receiving a castout command identifying a victim cache line castout from another cache memory, causes the victim cache line to be held in the cache array. If the other cache memory is a higher level cache in the cache hierarchy of the processor core, the cache controller marks the victim cache line in the cache directory so that it is less likely to be evicted by a replacement policy of the victim cache, and otherwise, marks the victim cache line in the cache directory so that it is more likely to be evicted by the replacement policy of the victim cache.
摘要翻译：受害者缓存存储器包括缓存阵列，高速缓存阵列的内容的高速缓存目录以及控制受害者缓存存储器的操作的高速缓存控制器。高速缓存控制器响应于从另一高速缓冲存储器接收识别受害者高速缓存线路突发的丢弃命令，使受害者高速缓存行保持在高速缓存阵列中。如果其他高速缓冲存储器是处理器核心的高速缓存层级中的较高级缓存，则高速缓存控制器将高速缓存目录中的受害者高速缓存行标记为不太可能被受害缓存的替换策略驱逐，否则，将缓存目录中的受害者缓存行标记为更有可能被受害者缓存的替换策略驱逐。

8. 发明申请

US20100153647A1 Cache-To-Cache Cast-In 失效
标题翻译：缓存到缓存注入
公开(公告)号：US20100153647A1
公开(公告)日：2010-06-17
申请号：US12335975
申请日：2008-12-16
申请人： Guy L. Guthrie , Alvan W. Ng , Michael S. Siegel , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： Guy L. Guthrie , Alvan W. Ng , Michael S. Siegel , William J. Starke , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0804 , G06F12/0831 , G06F12/0862
摘要： A data processing system includes a first processing unit and a second processing unit coupled by an interconnect fabric. The first processing unit has a first processor core and associated first upper and first lower level caches, and the second processing unit has a second processor core and associated second upper and lower level caches. In response to a data request, a victim cache line is selected for castout from the first lower level cache. The first processing unit issues on the interconnect fabric a lateral castout (LCO) command that identifies the victim cache line to be castout from the first lower level cache and indicates that a lower level cache is an intended destination. In response to a coherence response indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.
摘要翻译：数据处理系统包括由互连结构耦合的第一处理单元和第二处理单元。第一处理单元具有第一处理器核心和相关联的第一上部和第一下层高速缓存，并且第二处理单元具有第二处理器核心和相关联的第二上部和下部高速缓存。响应于数据请求，选择受害者高速缓存行用于从第一较低级别缓存进行舍弃。第一处理单元在互连结构上发出横向聚合（LCO）命令，该命令标识要从第一较低级缓存中抛出的受害缓存行，并且指示较低级缓存是预期目的地。响应于指示LCO命令的成功的一致性响应，从第一低级缓存中删除受害者高速缓存行并保存在第二较低级高速缓存中。

9. 发明授权

US07710874B2 System and method for automatic management of many computer data processing system pipes 有权
标题翻译：许多计算机数据处理系统管道的自动管理系统和方法
公开(公告)号：US07710874B2
公开(公告)日：2010-05-04
申请号：US10454052
申请日：2003-06-04
申请人： Ganesh Balakrishnan , Everett A. Corl, Jr. , Clark D. Jeffries , Ravinder K. Sabhikhi , Michael S. Siegel , Raj K. Singh , Rama M. Yedavalli
发明人： Ganesh Balakrishnan , Everett A. Corl, Jr. , Clark D. Jeffries , Ravinder K. Sabhikhi , Michael S. Siegel , Raj K. Singh , Rama M. Yedavalli
IPC分类号： H04L1/00
CPC分类号： H04L41/0896
摘要： A process control method and system including partitioning transmit decisions and certain measurements into one logical entity (Data Plane) and partitioning algorithm computation to update transmit probabilities into a second logical entity (Control Plane), the two entities periodically communicating fresh measurements from Data Plane to Control Plane and adjusted transmit probabilities from Control Plane to Data Plane. The transmit probability may be used in transmit/discard decisions of packets or instructions exercised at every arrival of a packet or instruction. In an alternative embodiment, the transmit probability may be used in transmit/delay decisions of awaiting instructions or packets exercised at every service event.
摘要翻译：一种过程控制方法和系统，包括将发送决策和某些测量划分成一个逻辑实体（数据平面）和分区算法计算，以将发送概率更新为第二逻辑实体（控制平面），所述两个实体周期性地将新的测量从数据平面传送到控制平面和从控制平面到数据平面的调整传输概率。发送概率可以用于在分组或指令的每个到达时所执行的分组或指令的发送/丢弃决定。在替代实施例中，发送概率可以用于在每个服务事件处等待指令或分组执行的发送/延迟决定。

10. 发明申请

US20080195774A1 STRUCTURE FOR AN ASYNCHRONOUS DATA INTERFACE 有权
标题翻译：异构数据接口的结构
公开(公告)号：US20080195774A1
公开(公告)日：2008-08-14
申请号：US12105449
申请日：2008-04-18
申请人： Scott J. Lemke , Kevin N. Magill , Michael S. Siegel
发明人： Scott J. Lemke , Kevin N. Magill , Michael S. Siegel
IPC分类号： G06F13/00
CPC分类号： G06F13/4059
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design, the design structure comprising for an interface system is disclosed. The system includes a buffer that receives data from a source in a first clock domain and stores the data to be read by a destination in a second clock domain, wherein the buffer functions in both the first clock domain and the second clock domain; a write pointer that points to data written by the source; and a read pointer that points to data read by the destination. According to the design structure, the write pointer and the read pointer are utilized to enable the data to be transmitted from the first clock domain to the second clock domain asynchronously.
摘要翻译：公开了一种体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构，包括用于接口系统的设计结构。该系统包括缓冲器，其从第一时钟域中的源接收数据，并将要由目的地读取的数据存储在第二时钟域中，其中缓冲器在第一时钟域和第二时钟域两者中起作用; 一个写入指针，指向由源写入的数据; 以及指向目的地读取的数据的读指针。根据设计结构，写指针和读指针被用于使数据能够异步地从第一时钟域发送到第二时钟域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式