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    • 8. 发明授权
    • System and method of channel serialization in a safety I/O product
    • 安全I / O产品中通道序列化的系统和方法
    • US07319406B2
    • 2008-01-15
    • US11240714
    • 2005-09-30
    • Joseph G. VazachEdward C. HopsecgerAnthony G. GibartDavid A. Vasko
    • Joseph G. VazachEdward C. HopsecgerAnthony G. GibartDavid A. Vasko
    • G08B21/00
    • G05B19/0425G05B2219/25153G05B2219/25157G05B2219/25158
    • A system serializes control signals within a safety control architecture wherein a safety serial interface at least one of receives and transmits signals from one or more processing components. A serialization component receives and serializes at least one data packet from the safety serial interface to control at least one of an input and an output associated with the safety control architecture. A safety related test circuit verifies input signals associated with the serialization component are not internally falsifying the state of the input signals. A heartbeat watchdog component verifies a true heartbeat bit in the at least one data packet is opposite a complement heartbeat bit in the at least one data packet within a predetermined time interval and shuts off power to at least one of an output and an input if such a condition is not met.
    • 系统在安全控制架构内对控制信号进行串行化,其中安全串行接口至少一个接收和发送来自一个或多个处理部件的信号。 序列化组件从安全串行接口接收并串行化至少一个数据分组,以控制与安全控制架构相关联的输入和输出中的至少一个。 验证与串行化组件相关联的输入信号的安全相关测试电路在内部不会伪造输入信号的状态。 心跳监视器组件验证至少一个数据分组中的真实心跳比特在预定时间间隔内与至少一个数据分组中的补码心跳比特相反,并且如果这样的话,则将其切换到输出和输入中的至少一个 条件不符合。
    • 9. 发明授权
    • Programmable controller module rack with a relative rack slot addressing
mechanism
    • 可编程控制器模块机架,具有相对机架插槽寻址机制
    • US5038317A
    • 1991-08-06
    • US223312
    • 1988-07-25
    • John E. CallanAnthony G. GibartKazuaki KumeShigeru Ina
    • John E. CallanAnthony G. GibartKazuaki KumeShigeru Ina
    • G06F13/14G05B19/048G05B19/05G06F11/22G06F12/06
    • G06F11/2289G05B19/054G06F12/0676
    • A programmable controller includes a number of equipment racks having slots which receive a processor module and a plurality of input/output modules. Each rack has a backplane which includes a number of buses for electrically interconnecting the modules therein, one of these buses carries slot address signals identifying the slot containing an input/output module which the processor module seeks to access. The backplanes of the racks are connected together in a daisy chain. Each backplane has a circuit which responds to the addresses of that rack's slots by producing enable signals for the module in the corresponding slot. This backplane circuit also subtracts the number of slots in its rack from the slot address and passes the result to the next rack in the daisy chain. By this justification of the slot address as it is passed down the daisy chain, each rack address decoder circuit can be hard wired to respond to slot addresses between zero and X, where X is the number of slots in that rack; regardless of the rack's relative position within the daisy chain and the range of virtual addresses for its slots.
    • 可编程控制器包括具有接收处理器模块和多个输入/输出模块的槽的多个设备机架。 每个机架具有背板,其包括用于将模块电连接到其中的多个总线,这些总线之一承载标识包含处理器模块寻求访问的输入/输出模块的时隙的时隙地址信号。 机架的背板以菊花链连接在一起。 每个背板都有一个电路,通过为相应插槽中的模块产生使能信号来响应该机架插槽的地址。 该背板电路还从插槽地址中减去其机架中的插槽数,并将结果传递给菊花链中的下一个机架。 通过插槽地址沿着菊花链传递的这种理由,每个机架地址解码器电路可以硬连线以响应零和X之间的时隙地址,其中X是该机架中的时隙数; 不管机架在菊花链中的相对位置以及其插槽的虚拟地址范围。