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1. 发明申请

US20110276766A1 CONFIGURABLE MEMORY CONTROLLER 审中-公开
标题翻译：可配置内存控制器
公开(公告)号：US20110276766A1
公开(公告)日：2011-11-10
申请号：US12774462
申请日：2010-05-05
申请人： Mark N. Fullerton , Sathish Kumar Radhakrishnan , Brent Mulholland , Ravi S. Setty , Lance Flake , Vinay Bhasin
发明人： Mark N. Fullerton , Sathish Kumar Radhakrishnan , Brent Mulholland , Ravi S. Setty , Lance Flake , Vinay Bhasin
IPC分类号： G06F12/00
CPC分类号： G06F1/3275 , G06F1/3206 , G06F1/3215 , G06F13/1626 , H04W52/0274 , Y02D10/13 , Y02D10/14 , Y02D70/142 , Y02D70/144
摘要： Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.
摘要翻译：控制对存储器的访问包括接收多个存储器访问请求并将相应的时间值分配给每个。基于时钟脉冲调整分配的时间值，并且生成优先权访问列表。考虑的因素包括错过访问期限，接近缺少访问截止日期以及页面是否打开。然后将最高排名的客户端传递给定序器以允许请求的访问。时间值可以根据客户端ID或客户端类型（延迟或带宽）进行分配和调整。定义了多个功率工作模式，其中所选择的功率操作模式中的操作至少部分地基于分配或调整的时间值。处理通过相关的逻辑电路并行（同时）在硬件中执行。

2. 发明授权

US06392935B1 Maximum bandwidth/minimum latency SDRAM interface 有权
标题翻译：最大带宽/最小延迟SDRAM接口
公开(公告)号：US06392935B1
公开(公告)日：2002-05-21
申请号：US09825201
申请日：2001-04-03
申请人： Brent Mulholland
发明人： Brent Mulholland
IPC分类号： G11C700
CPC分类号： G11C7/1072
摘要： A multi-bank dynamic random access memory (DRAM) device is configured such that the bandwidth for performing data transfers is increased and the latency when performing the operations is decreased. The memory device when incorporated in a computer system may be configured such that data requests are received from one or more other devices in the system for data transfer functions. Further, through the interleaving of access to the multiple banks within the memory array, various set-up functions are performed on one bank while data transfer functions are performed on another bank, thus effectively hiding such functions.
摘要翻译：多库动态随机存取存储器（DRAM）设备被配置为使得用于执行数据传输的带宽增加，并且执行操作时的等待时间减少。当存储器装置结合在计算机系统中时，可以被配置为使得数据请求从系统中的一个或多个其他装置接收以用于数据传送功能。此外，通过对存储器阵列内的多个存储体的访问的交织，在一个存储体上执行各种设置功能，同时在另一个存储体上执行数据传送功能，从而有效地隐藏这些功能。

3. 发明申请

US20080170685A1 Data scrambling circuit 审中-公开
标题翻译：数据加扰电路
公开(公告)号：US20080170685A1
公开(公告)日：2008-07-17
申请号：US11655685
申请日：2007-01-19
申请人： Lance Flake , Brent Mulholland
发明人： Lance Flake , Brent Mulholland
IPC分类号： H04L9/28
CPC分类号： G11B20/00086 , G06F21/72 , G11B20/0021 , G11B2020/1843 , G11B2220/2516
摘要： A data scrambling circuit is provided. The data scrambling circuit includes an integrated circuit having a digital logic device and an interface circuit coupled to the digital logic device. Also included is an external memory coupled to output pins on the interface circuit. The digital logic device communicates patterned data to the interface circuit. The interface circuit then scrambles the patterned data to produce a pseudo random output to be stored within the external memory and unscrambled a pseudo random signal from the external memory to produce unscrambled data to be read by the digital logic device.
摘要翻译：提供数据加扰电路。数据加扰电路包括具有数字逻辑器件和耦合到数字逻辑器件的接口电路的集成电路。还包括耦合到接口电路上的输出引脚的外部存储器。数字逻辑器件将图形数据传送到接口电路。然后，接口电路对图形化数据进行加扰，以产生要存储在外部存储器内的伪随机输出，并从外部存储器解扰一个伪随机信号，以产生未被数字逻辑器件读取的未加扰数据。

4. 发明申请

US20110276817A1 MEMORY POWER MANAGER 有权
标题翻译：内存电源管理器
公开(公告)号：US20110276817A1
公开(公告)日：2011-11-10
申请号：US12774479
申请日：2010-05-05
申请人： Mark N. Fullerton , Sathish Kumar Radhakrishnan , Brent Mulholland , Ravi S. Setty
发明人： Mark N. Fullerton , Sathish Kumar Radhakrishnan , Brent Mulholland , Ravi S. Setty
IPC分类号： G06F1/32 , G06F12/00 , G06F1/00
CPC分类号： G06F13/1668 , G06F1/3203 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.
摘要翻译：控制对存储器的访问包括接收多个存储器访问请求并将相应的时间值分配给每个。基于时钟脉冲调整分配的时间值，并且生成优先权访问列表。考虑的因素包括错过访问期限，接近缺少访问截止日期以及页面是否打开。然后将最高排名的客户端传递给定序器以允许请求的访问。时间值可以根据客户端ID或客户端类型（延迟或带宽）进行分配和调整。定义了多个功率工作模式，其中所选择的功率操作模式中的操作至少部分地基于分配或调整的时间值。处理通过相关的逻辑电路并行（同时）在硬件中执行。

5. 发明申请

US20070189084A1 Reduced pin count synchronous dynamic random access memory interface 审中-公开
标题翻译：减少引脚数同步动态随机存取存储器接口
公开(公告)号：US20070189084A1
公开(公告)日：2007-08-16
申请号：US11354028
申请日：2006-02-15
申请人： Brent Mulholland
发明人： Brent Mulholland
IPC分类号： G11C7/00 , G11C7/10 , G11C8/00
CPC分类号： G11C5/066 , G11C7/1072 , G11C8/12 , G11C8/18
摘要： A method is provided for reducing the number of conductive interfaces required to interface to a SDRAM. One or more conductive interfaces can be used, during a cycle, to both transfer data and provide a command or an address to an SDRAM. More specifically, each of the conductive interfaces on a controller can be used to control one data conductive interface and one of an address, bank address, RAS, CAS, or WE conductive interface on an SDRAM. The interface for the present invention provides a lower conductive interface count ASIC with a smaller package than a conventional SDRAM interface.
摘要翻译：提供了一种减少与SDRAM接口所需的导电接口数量的方法。在一个周期期间，可以使用一个或多个导电接口来传送数据并向SDRAM提供命令或地址。更具体地，控制器上的每个导电接口可用于控制一个数据导电接口以及SDRAM上的地址，组地址，RAS，CAS或WE导电接口中的一个。本发明的接口提供具有比常规SDRAM接口更小的封装的较低导电接口计数ASIC。

6. 发明授权

US08812889B2 Memory power manager 有权
标题翻译：内存电源管理器
公开(公告)号：US08812889B2
公开(公告)日：2014-08-19
申请号：US12774479
申请日：2010-05-05
申请人： Mark N. Fullerton , Sathish Kumar Radhakrishnan , Brent Mulholland , Ravi S. Setty
发明人： Mark N. Fullerton , Sathish Kumar Radhakrishnan , Brent Mulholland , Ravi S. Setty
IPC分类号： G06F1/26 , G06F1/32 , G06F13/16
CPC分类号： G06F13/1668 , G06F1/3203 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.
摘要翻译：控制对存储器的访问包括接收多个存储器访问请求并将相应的时间值分配给每个。基于时钟脉冲调整分配的时间值，并且生成优先权访问列表。考虑的因素包括错过访问期限，接近缺少访问截止日期以及页面是否打开。然后将最高排名的客户端传递给定序器以允许请求的访问。时间值可以根据客户端ID或客户端类型（延迟或带宽）进行分配和调整。定义了多个功率工作模式，其中所选择的功率操作模式中的操作至少部分地基于分配或调整的时间值。处理通过相关的逻辑电路并行（同时）在硬件中执行。

7. 发明申请

US20080005749A1 Hard disk controller having multiple, distributed processors 审中-公开
标题翻译：具有多个分布式处理器的硬盘控制器
公开(公告)号：US20080005749A1
公开(公告)日：2008-01-03
申请号：US11444583
申请日：2006-06-01
申请人： John P. Mead , Lance Flake , Kevin W. McGinnis , Brent Mulholland
发明人： John P. Mead , Lance Flake , Kevin W. McGinnis , Brent Mulholland
IPC分类号： G06F9/46
CPC分类号： G06F3/0658 , G06F3/061 , G06F3/0676
摘要： Hard disk controller having multiple, distributed processors. A novel approach is presented by which a separate and dedicated processor is provisioned to service each of a plurality of control loops within a hard disk drive (HDD) controller. For example, a first processor is implemented to service a servo control loop, a second processor is implemented to service channel interfacing, and a third processor is implemented to service host interfacing. In some embodiments, the channel and host interfacing are performed using protocol processors implemented within each of a disk manager module and a host manager module, respectively.
摘要翻译：具有多个分布式处理器的硬盘控制器。提出了一种新颖的方法，通过该方法提供单独的专用处理器来为硬盘驱动器（HDD）控制器内的多个控制环路中的每一个提供服务。例如，实现第一处理器以服务伺服控制环路，实施第二处理器来服务信道接口，并且第三处理器被实现为服务主机接口。在一些实施例中，使用分别在盘管理器模块和主机管理器模块中实现的协议处理器来执行信道和主机接口。

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