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    • 4. 发明授权
    • Double sided container process used during the manufacture of a semiconductor device
    • 在制造半导体器件期间使用的双面容器工艺
    • US07345333B2
    • 2008-03-18
    • US11496605
    • 2006-07-31
    • Scott J. DeBoerRonald A. WeimerJohn T. Moore
    • Scott J. DeBoerRonald A. WeimerJohn T. Moore
    • H01L27/108H01L29/76H01L29/94H01L31/119
    • H01L27/10888H01L21/76831H01L21/76895H01L27/10811H01L27/10817H01L27/10852H01L28/91H01L29/41725
    • A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact pads which contact a semiconductor wafer. A dielectric layer is provided over the wafer substrate assembly and etched to expose the digit line plug contact pads, and a liner is provided in the opening. A portion of the digit line plug is formed, then the dielectric layer is etched again to expose the capacitor storage cell contact pads. A capacitor bottom plate is formed to contact the storage cell contact pads, then the dielectric layer is etched a third time using the liner and the bottom plate as an etch stop layer. A capacitor cell dielectric layer and capacitor top plate are formed which provide a double-sided container cell. An additional dielectric layer is formed, then the additional dielectric layer, cell top plate, and the cell dielectric are etched to expose the digit line plug portion. Finally, a second digit line plug portion is formed to contact the first plug portion. A novel structure resulting from the inventive method is also discussed.
    • 在形成半导体器件期间使用的方法包括提供晶片衬底组件,其包括接触半导体晶片的多个数字线插头接触焊盘和电容器存储单元接触焊盘。 电介质层设置在晶片衬底组件上并被蚀刻以暴露数字线插头接触垫,并且衬套设置在开口中。 形成数字线插头的一部分,然后再次蚀刻电介质层以暴露电容器存储单元接触垫。 电容器底板形成为与存储单元接触焊盘接触,然后使用衬垫和底板作为蚀刻停止层,第三次蚀刻电介质层。 形成电容器单元电介质层和电容器顶板,其提供双面容器单元。 形成附加的电介质层,然后蚀刻附加的电介质层,电池顶板和电池电介质以露出数字线插头部分。 最后,形成第二数字线插头部分以接触第一插头部分。 还讨论了由本发明方法产生的新颖结构。
    • 6. 发明授权
    • Double sided container process used during the manufacture of a semiconductor device
    • 在制造半导体器件期间使用的双面容器工艺
    • US06696336B2
    • 2004-02-24
    • US09855217
    • 2001-05-14
    • Scott J. DeBoerRonald A. WeimerJohn T. Moore
    • Scott J. DeBoerRonald A. WeimerJohn T. Moore
    • H01L218242
    • H01L27/10888H01L21/76831H01L21/76895H01L27/10811H01L27/10817H01L27/10852H01L28/91H01L29/41725
    • A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact pads which contact a semiconductor wafer. A dielectric layer is provided over the wafer substrate assembly and etched to expose the digit line plug contact pads, and a liner is provided in the opening. A portion of the digit line plug is formed, then the dielectric layer is etched again to expose the capacitor storage cell contact pads. A capacitor bottom plate is formed to contact the storage cell contact pads, then the dielectric layer is etched a third time using the liner and the bottom plate as an etch stop layer. A capacitor cell dielectric layer and capacitor top plate is formed which provides a double-sided container cell. An additional dielectric layer is formed, then the additional dielectric layer, cell top plate, and the cell dielectric are etched to expose the digit line plug portion. Finally, a second digit line plug portion is formed to contact the first plug portion. A novel structure resulting from the inventive method is also discussed.
    • 在形成半导体器件期间使用的方法包括提供晶片衬底组件,其包括接触半导体晶片的多个数字线插头接触焊盘和电容器存储单元接触焊盘。 电介质层设置在晶片衬底组件上并被蚀刻以暴露数字线插头接触垫,并且衬套设置在开口中。 形成数字线插头的一部分,然后再次蚀刻电介质层以暴露电容器存储单元接触垫。 电容器底板形成为与存储单元接触焊盘接触,然后使用衬垫和底板作为蚀刻停止层,第三次蚀刻电介质层。 形成电容器电介质层和电容器顶板,其提供双面容器电池。 形成附加的电介质层,然后蚀刻附加的电介质层,电池顶板和电池电介质以露出数字线插头部分。 最后,形成第二数字线插头部分以接触第一插头部分。 还讨论了由本发明方法产生的新颖结构。
    • 8. 发明授权
    • Semiconductor wafer assemblies comprising photoresist over silicon nitride materials
    • 包括氮化硅材料上的光致抗蚀剂的半导体晶片组件
    • US06300671B1
    • 2001-10-09
    • US09376886
    • 1999-08-18
    • John T. MooreScott J. DeBoerMark Fischer
    • John T. MooreScott J. DeBoerMark Fischer
    • H01L2358
    • H01L21/31144G03F7/091H01L21/0214H01L21/0217H01L21/02211H01L21/02271H01L21/02304H01L21/312
    • In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer. In another aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; c) forming a photoresist over and against the barrier layer; d) exposing the photoresist to a patterned beam of light to render at least one portion of the photoresist more soluble in a solvent than an other portion, the barrier layer being an antireflective surface that absorbs light passing through the photoresist; and e) exposing the photoresist to the solvent to remove the at least one portion while leaving the other portion over the barrier layer. In yet another aspect, the invention includes a semiconductor wafer assembly, comprising: a) a silicon nitride material, the material having a surface; b) a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) a photoresist over and against the barrier layer.
    • 一方面,本发明包括半导体处理方法,包括:a)提供具有表面的氮化硅材料; b)在所述材料的表面上形成阻挡层,所述阻挡层包含硅和氮; 以及c)在所述阻挡层上形成光致抗蚀剂。 另一方面,本发明包括半导体处理方法,包括:a)提供具有表面的氮化硅材料; b)在所述材料的表面上形成阻挡层,所述阻挡层包含硅和氮; c)在阻挡层上形成光致抗蚀剂; d)将所述光致抗蚀剂暴露于图案化的光束以使所述光致抗蚀剂的至少一部分在溶剂中比其它部分更易溶,所述阻挡层是吸收通过所述光致抗蚀剂的光的抗反射表面; 以及e)将所述光致抗蚀剂暴露于所述溶剂以除去所述至少一个部分,同时将所述另一部分留在所述阻挡层上。 在另一方面,本发明包括半导体晶片组件,包括:a)氮化硅材料,该材料具有表面; b)在所述材料的表面上的阻挡层,所述阻挡层包含硅和氮; 以及c)在所述阻挡层上并抵靠所述阻挡层的光致抗蚀剂。
    • 9. 发明授权
    • Semiconductor wafer assemblies comprising silicon nitride, methods of
forming silicon nitride, and methods of reducing stress on
semiconductive wafers
    • 包括氮化硅的半导体晶片组件,形成氮化硅的方法以及减少半导体晶片上的应力的方法
    • US6093956A
    • 2000-07-25
    • US100530
    • 1998-06-18
    • John T. MooreScott J. DeBoerMark Fischer
    • John T. MooreScott J. DeBoerMark Fischer
    • H01L21/318H01L21/32H01L21/762H01L29/76H01L23/16
    • H01L21/3185H01L21/32H01L21/76202
    • In one aspect, the invention includes a method of semiconductive wafer processing comprising forming a silicon nitride layer over a surface of a semiconductive wafer, the silicon nitride layer comprising at least two portions, one of the at least two portions generating a compressive force against the other of the at least two portions, and the other of the at least two portions generating a tensile force against the one of the at least two portions. In another aspect, the invention includes a method of reducing stress on semiconductive wafer, the semiconductive wafer having a pair of opposing surfaces and having more silicon nitride over one of the opposing surfaces than over the other of the opposing surfaces, the method comprising providing the silicon nitride over the one of the opposing surfaces to comprise a first portion, a second portion and a third portion, the first, second and third portions being elevationally displaced relative to one another, the second portion being between the first and third portions, the second portion having a greater stoichiometric amount of silicon than the first and third portions, the semiconductive wafer being subjected to less stress than if the silicon nitride over the one of the opposing surfaces had a constant stoichiometric amount of silicon throughout its thickness. In yet other aspects, the invention includes semiconductive wafer assemblies.
    • 一方面,本发明包括一种半导体晶片处理方法,包括在半导体晶片的表面上形成氮化硅层,所述氮化硅层包括至少两个部分,所述至少两个部分中的一个部分产生抵抗 所述至少两个部分中的另一个,并且所述至少两个部分中的另一部分产生相对于所述至少两个部分中的一个部分的张力。 在另一方面,本发明包括减少半导体晶片上的应力的方法,该半导体晶片具有一对相对的表面,并且在相对表面的一个之上具有比另一个相对表面更多的氮化硅,该方法包括提供 所述相对表面中的一个上的氮化硅包括第一部分,第二部分和第三部分,所述第一部分,第二部分和第三部分相对于彼此正向移位,所述第二部分位于第一部分和第三部分之间, 第二部分具有比第一和第三部分更大的化学计算量的硅,与相对表面上的一个相反的表面上的氮化硅在整个厚度上具有恒定的化学计量的硅时,半导体晶片受到的应力较小。 在另一方面,本发明包括半导体晶片组件。