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1. 发明授权

US5490261A Interlock for controlling processor ownership of pipelined data for a store in cache 失效
标题翻译：用于控制缓存中存储的流水线数据的处理器所有权的联锁
公开(公告)号：US5490261A
公开(公告)日：1996-02-06
申请号：US680176
申请日：1991-04-03
申请人： Bradford M. Bean , Anne E. Bierce , Neal T. Christensen , Leo J. Clark , Steven T. Comfort , Christine C. Jones , Pak-Kin Mak
发明人： Bradford M. Bean , Anne E. Bierce , Neal T. Christensen , Leo J. Clark , Steven T. Comfort , Christine C. Jones , Pak-Kin Mak
IPC分类号： G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0811
摘要： Insures data integrity in process ownership indications by providing an ownership interlock on the data units in a pipeline to a store-in type of cache. An ownership interlock prevents any processor ownership change to occur (i.e. exclusive or readonly ownership) for a cache data unit until all outstanding stores have been made in the cache data unit, after which the ownership may be changed. An ownership change may be signalled by a cross-invalidate (XI) signal to a processor. Outstanding stores are received by the pipeline after the stores are completed by a processor, and the outstanding stores output from the pipeline into a store-in cache. A continuous flow of stores is enabled into and out of the pipeline to expedite a change of ownership requested of a data unit in the cache. The continuous flow avoids having to stop a processor from putting stores into the pipeline and avoids forcing all outstanding stores out of the pipeline into the cache before indicating a change of processor ownership.
摘要翻译：通过在流水线中的数据单元上提供所有权互锁到存储型缓存来保护进程所有权指示中的数据完整性。所有权互锁防止对高速缓存数据单元发生任何处理器所有权改变（即，独占或只读所有权），直到所有未完成的存储已经在高速缓存数据单元中进行，之后可以改变所有权。所有权变更可以通过交叉无效（XI）信号发送给处理器。在存储由处理器完成之后，流水线接收到未完成的存储，并且从流水线输出的未完成存储到存储缓存中。连续的商店流程被启用进出管道，以加快对高速缓存中数据单元所需的所有权的更改。连续流程避免了停止处理器将存储放入流水线中，并避免在指示处理器所有权的更改之前将所有未完成的存储从管道中强制进入高速缓存。

2. 发明授权

US4916703A Handling errors in the C bit of a storage key 失效
标题翻译：处理存储密钥的C位中的错误
公开(公告)号：US4916703A
公开(公告)日：1990-04-10
申请号：US276736
申请日：1988-11-28
申请人： Neal T. Christensen , Steven T. Comfort , Robert J. Hurban , Bruce L. McGilvray , Arthur J. Sutton , James R. Urquhart , David R. Willoughby
发明人： Neal T. Christensen , Steven T. Comfort , Robert J. Hurban , Bruce L. McGilvray , Arthur J. Sutton , James R. Urquhart , David R. Willoughby
IPC分类号： G06F11/10 , G06F11/00
CPC分类号： G06F11/00 , G06F11/10
摘要： A method of handling errors in the C bit of a storage key by modifying the INSERT STORAGE KEY (ISK) and the RESET REFERENCE BIT (RRB) instructions. If an error is found in the C bit during the execution of these instructions, microcode is instructed to refresh the C bit. The C bit is interrogated a second time to determine if the refreshed C bit is still in error. If the refreshed C bit is not in error a second time, then the first error was caused by a soft or transient error, and the instruction is continued. If the refreshed C bit is in error a second time then the first and second errors were caused by a permanent error such as a stuck bit, and a system recovery machine check error is generated. The handling of C bit errors is thus done in a dynamic fashion as the instructions are executed.

3. 发明授权

US08706469B2 Method and apparatus for increasing the efficiency of an emulation engine 有权
标题翻译：提高仿真引擎效率的方法和装置
公开(公告)号：US08706469B2
公开(公告)日：2014-04-22
申请号：US11344058
申请日：2006-01-31
申请人： William F. Beausoleil , Steven T. Comfort , Beshara G. Elmufdi
发明人： William F. Beausoleil , Steven T. Comfort , Beshara G. Elmufdi
IPC分类号： G06F9/455 , G06F17/50 , G06F13/10
CPC分类号： G06F17/5027 , G06F13/105 , G06F15/173 , G06F17/5054
摘要： A method and apparatus for improving the efficiency of a processor-based emulation engine. The emulation engine is composed of a plurality of processors, each processor capable of emulating a logic gate. Processors are arranged into groups of processors called clusters. Each processor receives inputs, processes the inputs, and stores the outputs in an output array. The output array allows processors within a cluster to fetch an output from a processor that was written to the output array during a previous cycle. The output array can also store and transfer data between clusters of processors. Consequently, the number of cycles that a processor or a cluster has to wait to fetch data is greatly reduced and the efficiency of the emulation engine is increased.
摘要翻译：一种用于提高基于处理器的仿真引擎的效率的方法和装置。仿真引擎由多个处理器组成，每个处理器能够仿真逻辑门。处理器被布置成称为簇的处理器组。每个处理器接收输入，处理输入，并将输出存储在输出阵列中。输出阵列允许集群内的处理器在上一个周期内从处理器获取输出到写入输出数组的输出。输出阵列还可以在处理器集群之间存储和传输数据。因此，处理器或集群必须等待获取数据的周期数大大减少，并且仿真引擎的效率增加。

4. 发明授权

US5495587A Method for processing checkpoint instructions to allow concurrent execution of overlapping instructions 失效
标题翻译：用于处理检查点指令以允许并发执行重叠指令的方法
公开(公告)号：US5495587A
公开(公告)日：1996-02-27
申请号：US263497
申请日：1994-06-21
申请人： Steven T. Comfort , Clifford O. Hayden , John S. Liptay , Susan B. Stillman , Charles F. Webb
发明人： Steven T. Comfort , Clifford O. Hayden , John S. Liptay , Susan B. Stillman , Charles F. Webb
IPC分类号： G06F9/38 , G06F11/14
CPC分类号： G06F9/3863 , G06F11/1407
摘要： An instruction processing system and method which utilizes instruction completion to isolate errors, including those in the post-completion processing of operand stores, to an interval between checkpoints, while allowing the processing of checkpointing instructions to be overlapped with that of other instructions. Checkpoints are established before and after such instructions, and all processing (including that of operand stores) from before a checkpoint must be done prior to allowing instruction completion to move beyond the checkpoint. Nevertheless, instructions from beyond a checkpoint are allowed to be processed up to the point of completion while waiting for the checkpoint to be cleared. The point at which instructions must wait on a prior checkpoint is thus moved to the final phase of instruction processing (instruction completion), at significant performance advantage over a conventional implementation in which this waiting is done at instruction fetch, decode, or execution time.
摘要翻译：一种指令处理系统和方法，其使用指令完成将包括操作数存储器的后完成处理中的错误的错误隔离到检查点之间的间隔，同时允许检查点指令的处理与其他指令的处理重叠。在这些指令之前和之后建立检查点，并且必须在允许指令完成超出检查点之前完成检查点之前的所有处理（包括操作数存储的处理）。然而，在等待检查点被清除之前，允许超出检查点的指令被处理到完成点。因此，相对于在指令获取，解码或执行时间完成这种等待的常规实现，指令必须在先前检查点上等待的点被移动到指令处理（指令完成）的最后阶段。

5. 发明授权

US5495590A Checkpoint synchronization with instruction overlap enabled 失效
标题翻译：检查点同步与启用指令重叠
公开(公告)号：US5495590A
公开(公告)日：1996-02-27
申请号：US480107
申请日：1995-06-07
申请人： Steven T. Comfort , Clifford O. Hayden , John S. Liptay , Susan B. Stillman , Charles F. Webb
发明人： Steven T. Comfort , Clifford O. Hayden , John S. Liptay , Susan B. Stillman , Charles F. Webb
IPC分类号： G06F9/38 , G06F11/14
CPC分类号： G06F9/3863 , G06F11/1407
摘要： An instruction processing system and method which utilizes instruction completion to isolate errors, including those in the post-completion processing of operand stores, to an interval between checkpoints, while allowing the processing of checkpointing instructions to be overlapped with that of other instructions. Checkpoints are established before and after such instructions, and all processing (including that of operand stores) from before a checkpoint must be done prior to allowing instruction completion to move beyond the checkpoint. Nevertheless, instructions from beyond a checkpoint are allowed to be processed up to the point of completion while waiting for the checkpoint to be cleared. The point at which instructions must wait on a prior checkpoint is thus moved to the final phase of instruction processing (instruction completion), at significant performance advantage over a conventional implementation in which this waiting is done at instruction fetch, decode, or execution time.
摘要翻译：一种指令处理系统和方法，其使用指令完成将包括操作数存储器的后完成处理中的错误的错误隔离到检查点之间的间隔，同时允许检查点指令的处理与其他指令的处理重叠。在这些指令之前和之后建立检查点，并且必须在允许指令完成超出检查点之前完成检查点之前的所有处理（包括操作数存储的处理）。然而，在等待检查点被清除之前，允许超出检查点的指令被处理到完成点。因此，相对于在指令获取，解码或执行时间完成这种等待的常规实现，指令必须在先前检查点上等待的点被移动到指令处理（指令完成）的最后阶段。

6. 发明授权

US5257354A System for monitoring and undoing execution of instructions beyond a serialization point upon occurrence of in-correct results 失效
标题翻译：用于在出现正确结果后监视和撤销指令超出序列化点执行的系统
公开(公告)号：US5257354A
公开(公告)日：1993-10-26
申请号：US641987
申请日：1991-01-16
申请人： Steven T. Comfort , John S. Liptay , Charles F. Webb
发明人： Steven T. Comfort , John S. Liptay , Charles F. Webb
IPC分类号： G06F9/38 , G06F11/28 , G06F9/30 , G06F11/30
CPC分类号： G06F9/3836 , G06F9/3861
摘要： A system whereby a central processor continues operation beyond a serialization point before the architecture defines that it is permissible to do so. According to the system, it is ascertained whether correct results are being achieved after the serializing point. If some doubt develops about the correctness of the results, the processor is returned to its status at the serialization point and the processing is repeated. In one embodiment, correctness of results is determined by way of a monitoring mechanism which depends on the fact that interactions between CPUs are confined to references to storage. The operations which are performed prior to the time that the architecture allows them, are restricted to ones which depend on fetches made from storage. The needed assurance of correct operation is gained by monitoring the storage locations from which fetches are made on behalf of instructions which logically follow the serializing operation, but which are made prior to the time that fetching is allowed to resume. If those storage locations are not changed during the time between when the first such fetch is actually made from one of them, and the time that fetching is allowed to resume, then the results of the processing which was done by the CPU (based on those fetches) must be exactly the same as if all of the fetches and processing was done in a single instant at the moment that the fetches became allowed.

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