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1. 发明授权

US4916703A Handling errors in the C bit of a storage key 失效
标题翻译：处理存储密钥的C位中的错误
公开(公告)号：US4916703A
公开(公告)日：1990-04-10
申请号：US276736
申请日：1988-11-28
申请人： Neal T. Christensen , Steven T. Comfort , Robert J. Hurban , Bruce L. McGilvray , Arthur J. Sutton , James R. Urquhart , David R. Willoughby
发明人： Neal T. Christensen , Steven T. Comfort , Robert J. Hurban , Bruce L. McGilvray , Arthur J. Sutton , James R. Urquhart , David R. Willoughby
IPC分类号： G06F11/10 , G06F11/00
CPC分类号： G06F11/00 , G06F11/10
摘要： A method of handling errors in the C bit of a storage key by modifying the INSERT STORAGE KEY (ISK) and the RESET REFERENCE BIT (RRB) instructions. If an error is found in the C bit during the execution of these instructions, microcode is instructed to refresh the C bit. The C bit is interrogated a second time to determine if the refreshed C bit is still in error. If the refreshed C bit is not in error a second time, then the first error was caused by a soft or transient error, and the instruction is continued. If the refreshed C bit is in error a second time then the first and second errors were caused by a permanent error such as a stuck bit, and a system recovery machine check error is generated. The handling of C bit errors is thus done in a dynamic fashion as the instructions are executed.

2. 发明授权

US5274646A Excessive error correction control 失效
标题翻译：过大的纠错控制
公开(公告)号：US5274646A
公开(公告)日：1993-12-28
申请号：US686721
申请日：1991-04-17
申请人： Thomas M. Brey , Matthew A. Krygowski , Bruce L. McGilvray , Trinh H. Nguyen , William W. Shen , Arthur J. Sutton
发明人： Thomas M. Brey , Matthew A. Krygowski , Bruce L. McGilvray , Trinh H. Nguyen , William W. Shen , Arthur J. Sutton
IPC分类号： G06F11/10 , G06F11/07 , G06F11/16 , G06F12/16
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/0793 , G06F11/1048 , G06F11/167
摘要： A method of automatically invoking a recoverable and fault tolerant implementation of the complemented/recomplemented (C/R) error correction method without the assistance of a service processor when an excessive error is detected in main storage (MS) by ECC logic circuits. An excessive error is not correctable by the ECC. These novel changes to the C/R method increase its effectiveness and protect the C/R hardware against random failure. Further, if an excessive error is corrected in a page in MS, an excessive error reporting process is provided for controlling the reporting using a storage map to determine if a previous correction in that page has been reported. If it has been reported, then no further reporting of soft excessive errors is made for that page. A service processor is signaled in parallel to update its persistent copy of the storage map so that on a next initializations of MS the memory map can be restored in the memory. The memory map is used to assist the repair of failing parts of MS, and is reset after MS is repaired.
摘要翻译：一种在由ECC逻辑电路在主存储器（MS）中检测到过大的错误的情况下，无需服务处理器的协助，自动调用补充/重新补码（C / R）纠错方法的可恢复和容错实现的方法。 ECC不能纠正过大的错误。 C / R方法的这些新变化提高了其有效性，并保护C / R硬件免受随机故障的影响。此外，如果在MS中的页面中校正了过多的错误，则提供了过多的错误报告处理，用于使用存储映射来控制报告，以确定是否已经报告了该页面中的先前校正。如果已经报告，则不会再为该页面报告软过度错误。服务处理器并行发信号以更新其存储映射的持久副本，以便在MS的下一个初始化时，可以在存储器中恢复存储器映射。存储器映射用于协助修复MS故障部件，并在MS修复后重置。

3. 发明授权

US4456954A Virtual machine system with guest architecture emulation using hardware TLB's for plural level address translations 失效
标题翻译：虚拟机系统与客户体系结构仿真使用硬件TLB进行多级地址转换
公开(公告)号：US4456954A
公开(公告)日：1984-06-26
申请号：US273532
申请日：1981-06-15
申请人： Robert J. Bullions, III , Thomas O. Curlee, III , Peter H. Gum , Bruce L. McGilvray , Ethel L. Richardson
发明人： Robert J. Bullions, III , Thomas O. Curlee, III , Peter H. Gum , Bruce L. McGilvray , Ethel L. Richardson
IPC分类号： G06F9/44 , G06F9/455 , G06F9/46 , G06F12/10 , G06F9/32
CPC分类号： G06F12/1063 , G06F9/44 , G06F9/45558 , G06F2009/45566 , G06F2009/45583
摘要： Translation look aside buffer (TLB) hardware is provided in a central processor (CP) that receives the results of double-level address translations to eliminate the need for having shadow tables for the second-level in a virtual machine (VM) environment. Hardware is provided for indicating whether a requested address sent by the CP Instruction Execution (IE) unit for translation is a guest or host/native request, and for a guest request whether it is a real or virtual address. Intermediate translations for a double-level translation may or may not be inhibited from being loaded into the TLB. Guest entries may be purged from the TLB without disturbing any host entries. An accelerated preferred guest mode in the CP forces single-level translation hardware to translate each accelerated preferred guest request. A non-accelerated guest request may instead be translated by microcode. A limit check register is provided to check preferred guest addresses without causing performance degradation.
摘要翻译：在中央处理器（CP）中提供翻译旁边缓冲器（TLB）硬件，中央处理器（CP）接收双层地址转换的结果，以消除在虚拟机（VM）环境中为第二级提供影子表的需要。硬件被提供用于指示用于转换的CP指令执行（IE）单元发送的请求地址是来宾还是主机/本机请求，以及客户请求是否为真实或虚拟地址。双级转换的中间翻译可能被禁止或不被禁止加载到TLB中。访客条目可以从TLB清除，而不会干扰任何主机条目。 CP中加速的首选访客模式迫使单级转换硬件翻译每个加速的首选客人请求。非加速访客请求可能会被微代码翻译。提供限制检查寄存器来检查优先访客地址，而不会导致性能下降。

4. 发明授权

US4400770A Cache synonym detection and handling means 失效
公开(公告)号：US4400770A
公开(公告)日：1983-08-23
申请号：US205486
申请日：1980-11-10
申请人： Shiu K. Chan , John A. Gerardi , Bruce L. McGilvray
发明人： Shiu K. Chan , John A. Gerardi , Bruce L. McGilvray
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0802
摘要： The disclosure detects and handles synonyms for a store-in-cache (SIC). A processor cache directory (PD) is searched in a principle class addressed by a subset of bits taken from a processor request's logical address. The class address has both translatable and non-translatable bits. If any of the set-associative line entries in the principle class contains the request's translated address, the data is accessed in a corresponding line location in the cache. If the principle class does not have any entry with the request's translated address, a cache miss signal occurs which causes a line fetch command to be generated for main storage to fetch the required line. The line fetch command also causes synonym search circuits to generate the address of every potential synonym class by permutating the translatable bits in the principle class address provided in the line fetch command. Then each potential synonym class is accessed in a copy directory (CD) (which is a copy of essential information in all entries in PD) and compared to the translated request address in order to detect for any existing synonym. Each line entry in the PD and CD also has an exclusive (EX) shareability control bit which controls the handling of a request after detection of a synonym in the CD. If the EX bit is off representing a read only (RO) state, the line cannot be locked during any checkpoint interval. Then the data is not accessed in the detected synonym location, but instead the RO line is copied into an entry in the principle class to improve system performance due to subsequent requests expected to the same line. The synonym line is not invalidated unless the processor is requesting the data exclusively (EX). If the EX bit is on representing an exclusive state in a found synonym entry, the line may be locked in the cache during a checkpoint interval, and therefore the data is accessed in the detected synonym location in the SIC because it cannot then be moved.

5. 发明授权

US4394731A Cache storage line shareability control for a multiprocessor system 失效
标题翻译：多处理器系统的缓存存储线可共享性控制
公开(公告)号：US4394731A
公开(公告)日：1983-07-19
申请号：US205500
申请日：1980-11-10
申请人： Frederick O. Flusche , Richard N. Gustafson , Bruce L. McGilvray
发明人： Frederick O. Flusche , Richard N. Gustafson , Bruce L. McGilvray
IPC分类号： G06F12/08 , G06F15/16
CPC分类号： G06F12/0815
摘要： A multiprocessor (MP) system is described having central processors (CPs) in which each CP has a store-in-cache (SIC) with an associated processor directory (PD). Each PD has a plurality of line entries which define the content of corresponding line positions in the associated SIC. Each line entry has an associated data shareability control bit, designated EX, which may be set to a one or zero state to indicate, respectively, the exclusive (EX) or readonly (RO) state of the associated line. An exclusive line is not shareable, but a readonly line is shareable i.e. may exist validly in more than one SIC in the MP. Any CP in the MP can request data in an EX state from its SIC, which data may or may not be found in its SIC or in another CP's SIC. If a CP requests a line of storage data in EX state and the line is found in EX state in another CP's SIC, it may be allowed to remain in the other CP's SIC by being set to RO state in both CPU SICs for the situations in which: (1) the line is found unchanged in EX state in the other CP's SIC, or (2) the line is found in RO state in the other CP's SIC, in which case the line is received and set to RO state in the requesting SIC even though requested in EX state. But if the line is found to be changed in the other CP's SIC, its shareability designation in the requesting SIC will be EX and the line is invalidated in the other CP's SIC from where it is castout.
摘要翻译：描述了具有中央处理器（CP）的多处理器（MP）系统，其中每个CP具有与相关联的处理器目录（PD）的高速缓存存储器（SIC）。每个PD具有多个行条目，其定义相关SIC中相应行位置的内容。每个行条目具有指定为EX的相关联的数据共享性控制位，其可以被设置为一个或零个状态，以分别指示相关行的排他（EX）或只读（RO）状态。独占行不可共享，但只读行可共享，即可以在MP中的多个SIC中有效存在。 MP中的任何CP可以从其SIC请求EX状态的数据，哪些数据可能在其SIC或另一个CP的SIC中可能找到。如果CP在EX状态下请求一行存储数据，并且在另一个CP的SIC中在EX状态下发现该行，则可以通过在两个CPU SIC中的情况下将其设置为RO状态来保留在其他CP的SIC中其中：（1）其他CP的SIC在EX状态下发现该行不变，或者（2）在另一个CP的SIC中发现该行在RO状态，在这种情况下，该行被接收并设置为RO状态即使在EX状态下请求SIC请求。但是，如果在其他CP的SIC中发现该行已被更改，则其请求的SIC中的可共享性指定将为EX，并且该线在其它CP的SIC中被放弃。

6. 发明授权

US4513367A Cache locking controls in a multiprocessor 失效
标题翻译：多处理器中的缓存锁定控件
公开(公告)号：US4513367A
公开(公告)日：1985-04-23
申请号：US246788
申请日：1981-03-23
申请人： Shiu K. Chan , John A. Gerardi , Bruce L. McGilvray
发明人： Shiu K. Chan , John A. Gerardi , Bruce L. McGilvray
IPC分类号： G06F12/08 , G06F12/12 , G06F15/16 , G06F15/177 , G06F13/08
CPC分类号： G06F12/0817 , G06F12/126
摘要： A lock array is provided with bit positions corresponding to each line entry in an associated cache directory. When a lock bit is on, it inhibits the castout, replacement, or invalidation of the associated cache line, which operations are allowed when the lock bit is off. The lock bit may be in an off state while an associated valid bit is set on, but once the lock bit is set on the valid bit cannot be set off until the lock bit is first set off. Lock array controls operate with a replacement selection circuit (which may be conventional) to eliminate each locked line from being a replacement candidate in its congruence class in a set-associative store-in-cache in a multiprocessor (MP). The lock array enables simultaneous reset of all lock bits at each checkpoint without disturbing the status of the associated cache directory. A special type of IE operand request, called a store-interrogate (SI) request, is used to lock the accessed line, whether or not the SI request hits or misses in the cache. Any locked line can continue to receive any fetch, SI, or store cache request from its own IE. Any line remains unlocked as long as it is not accessed by a SI request; that is a line remains unlocked as long as it only receives fetch requests, and fetch requests are generally much more numerous than SI requests. Line locking enables the castout or invalidation of unlocked cache lines during a checkpoint interval.
摘要翻译：锁阵列具有与相关联的高速缓存目录中的每个行条目相对应的位位置。当锁定位打开时，它禁止关联的高速缓存行的转换，替换或无效，当锁定位关闭时允许执行哪些操作。当相关的有效位置1时，锁定位可能处于关闭状态，但一旦锁定位置于有效位之后，才能先锁定锁定位。锁定阵列控制使用替换选择电路（可以是常规的）来消除每个锁定线在多处理器（MP）中的集合关联存储器中的等同类中的替换候选。锁定阵列可以在每个检查点同时复位所有锁定位，而不会干扰相关缓存目录的状态。使用特殊类型的IE操作数请求（称为存储询问（SI）请求）来锁定所访问的行，无论SI请求是否在缓存中命中或丢失。任何锁定的行可以继续从其自己的IE接收任何提取，SI或存储缓存请求。只要SI不被SI请求访问，任何行都将保持解锁; 只要它只接收提取请求，那么一行仍然是解锁的，并且提取请求通常比SI请求多得多。线路锁定可以在检查点间隔期间实现解锁或无效解锁的高速缓存行。

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