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1. 发明申请

US20220088392A1 Architectures for an Implantable Stimulator Device Having a Plurality of Electrode Driver Integrated Circuits with Shorted Electrode Outputs 有权
公开(公告)号：US20220088392A1
公开(公告)日：2022-03-24
申请号：US17457366
申请日：2021-12-02
申请人： Boston Scientific Neuromodulation Corporation
发明人： Emanuel Feldman , Jordi Parramon , Paul J. Griffith , Jess Shi , Robert Tong , Goran Marnfeldt
IPC分类号： A61N1/36 , A61N1/05
摘要： A new architecture is disclosed for an IPG having a master and slave electrode driver integrated circuits (ICs). The electrode outputs on the ICs are wired together. Each IC can be programmed to provide pulses with different frequencies. Active timing channels in master and slave ICs are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other IC so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.

2. 发明授权

US09925385B2 Timing channel circuitry for creating pulses in an implantable stimulator device 有权
公开(公告)号：US09925385B2
公开(公告)日：2018-03-27
申请号：US15289809
申请日：2016-10-10
申请人： Boston Scientific Neuromodulation Corporation
发明人： Paul J. Griffith , Goran N. Marnfeldt , Jordi Parramon
IPC分类号： A61N1/37 , A61N1/372 , A61N1/36
CPC分类号： A61N1/37264 , A61N1/36125 , A61N1/372 , A61N1/37252
摘要： Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.

3. 发明申请

US20160184591A1 Architectures for an Implantable Stimulator Device Having a Plurality of Electrode Driver Integrated Circuits with Shorted Electrode Outputs 审中-公开
公开(公告)号：US20160184591A1
公开(公告)日：2016-06-30
申请号：US15063072
申请日：2016-03-07
申请人： Boston Scientific Neuromodulation Corporation
发明人： Emanuel Feldman , Jordi Parramon , Paul J. Griffith , Jess Shi , Robert Tong , Goran Marnfeldt
IPC分类号： A61N1/36 , A61N1/05
CPC分类号： A61N1/36125 , A61N1/05 , A61N1/0534 , A61N1/36171 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73257 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00
摘要： Disclosed is a new architecture for an IPG having a master and slave electrode driver integrated circuits. The electrode outputs on the integrated circuits are wired together. Each integrated circuit can be programmed to provide pulses with different frequencies. Active timing channels in each of the master and slave integrated circuits are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other integrated circuit so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.

4. 发明申请

US20160082260A1 Architectures for an Implantable Medical Device System 审中-公开
标题翻译：可植入医疗器械系统的架构
公开(公告)号：US20160082260A1
公开(公告)日：2016-03-24
申请号：US14961649
申请日：2015-12-07
申请人： Boston Scientific Neuromodulation Corporation
发明人： Paul J. Griffith , Jordi Parramon , Goran Marnfeldt , Daniel Aghassian , Kiran Nimmagadda , Emanuel Feldman , Jess W. Shi
IPC分类号： A61N1/36 , A61N1/05
CPC分类号： A61N1/36125 , A61N1/025 , A61N1/0551 , A61N1/0553 , A61N1/36071
摘要： An improved architecture for an implantable medical device such as an implantable pulse generator (IPG) is disclosed. In one embodiment, the various functional blocks for the IPG are incorporated into a signal integrated circuit (IC). Each of the functional blocks communicates with each other, and with other off-chip devices if necessary, via a centralized bus governed by a communication protocol. To communicate with the bus and to adhere to the protocol, each circuit block includes bus interface circuitry adherent with that protocol. Because each block complies with the protocol, any given block can easily be modified or upgraded without affecting the design of the other blocks, facilitating debugging and upgrading of the IPG circuitry. Moreover, because the centralized bus can be taken off the integrated circuit, extra circuitry can easily be added off chip to modify or add functionality to the IPG.
摘要翻译：公开了一种用于植入式医疗装置（例如植入式脉冲发生器（IPG））的改进的架构。在一个实施例中，用于IPG的各种功能块被并入到信号集成电路（IC）中。每个功能块通过由通信协议管理的集中式总线彼此通信，并且如果需要，与其他片外设备通信。为了与总线进行通信并遵守协议，每个电路块包括与该协议相关的总线接口电路。由于每个块符合协议，任何给定的块都可以轻松修改或升级，而不影响其他块的设计，便于IPG电路的调试和升级。此外，由于集中式总线可以从集成电路中取出，所以额外的电路可以很容易地从芯片上添加到IPG中来修改或添加功能。

5. 发明授权

US09008790B2 Timing channel circuitry for creating pulses in an implantable stimulator device 有权
标题翻译：用于在可植入刺激器装置中产生脉冲的定时通道电路
公开(公告)号：US09008790B2
公开(公告)日：2015-04-14
申请号：US13847676
申请日：2013-03-20
申请人： Boston Scientific Neuromodulation Corporation
发明人： Paul J. Griffith , Goran N. Marnfeldt , Jordi Parramon
IPC分类号： A61N1/05 , A61N1/372 , A61N1/36
CPC分类号： A61N1/37264 , A61N1/36125 , A61N1/372 , A61N1/37252
摘要： Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.
摘要翻译：公开了一种用于控制可植入刺激器中的刺激电路的定时通道电路。定时通道电路包括可寻址存储器。所需脉冲的各个相位的数据使用不同数量的字存储在存储器中，包括表示相位中的字数的命令，存储在存储器中的下一相的下一个地址，以及脉冲宽度或当前阶段的持续时间，刺激电路的控制数据，脉冲幅度和电极数据。命令数据用于通过地址总线对当前阶段中的字进行寻址，哪些字被发送到用于刺激电路的控制寄存器。在当前阶段的脉冲宽度持续时间过去之后，存储的下一个地址用于访问存储在存储器中的下一个相位的数据。

6. 发明申请

US20140194947A1 Current Generation Architecture for an Implantable Stimulator Device Having Coarse and Fine Current Control 审中-公开
标题翻译：具有粗细电流控制的植入式刺激器装置的当前一代架构
公开(公告)号：US20140194947A1
公开(公告)日：2014-07-10
申请号：US14203120
申请日：2014-03-10
申请人： Boston Scientific Neuromodulation Corporation
发明人： Jordi Parramon , David K.L. Peterson , Paul J. Griffith
IPC分类号： A61N1/36
CPC分类号： A61N1/36125 , A61N1/0531 , A61N1/0534 , A61N1/0541 , A61N1/0543 , A61N1/0551 , A61N1/36071
摘要： Disclosed herein are current output architectures for implantable stimulator devices. Current source and sink circuitry is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking an amount of current to or from any one of the electrodes of the device. The current source circuitry is distinct from the current sink circuitry, and the two share no common circuit nodes prior to connection to the electrodes. In other words, the current source circuitry and the current sink circuitry do not share a common node other than the electrodes. Each stage is preferably formed of a current mirror for receiving a reference current and outputting a scaled version of current to that stage's switch bank. The scalar at each stage can be set by wiring a desired number of output transistors in parallel.
摘要翻译：这里公开了用于可植入刺激装置的电流输出结构。电流源和接收电路被分成多个级，其中每个级能够经由相关联的开关组来产生或吸收来自该器件的任何一个电极的电流量。电流源电路与当前的吸收电路不同，并且两者在连接到电极之前不共享公共电路节点。换句话说，电流源电路和电流吸收电路不共享电极以外的公共节点。每个级最好由用于接收参考电流的电流镜形成，并将电流的缩放版本输出到该级的开关组。可以通过并联连接所需数量的输出晶体管来设置每一级的标量。

7. 发明申请

US20180178012A1 Current Generation Architecture for an Implantable Stimulator Device Having Coarse and Fine Current Control 审中-公开
公开(公告)号：US20180178012A1
公开(公告)日：2018-06-28
申请号：US15903775
申请日：2018-02-23
申请人： Boston Scientific Neuromodulation Corporation
发明人： Jordi Parramon , David K.L. Peterson , Paul J. Griffith
IPC分类号： A61N1/36 , A61N1/05
CPC分类号： A61N1/36125 , A61N1/0531 , A61N1/0534 , A61N1/0541 , A61N1/0543 , A61N1/0551 , A61N1/36071
摘要： A current generation architecture for an implantable stimulator device such as an Implantable Pulse Generator (IPG) is disclosed. Current source and sink circuitry are both divided into coarse and fine portions, which respectively can provide coarse and fine current resolutions to a specified electrode on the IPG. The coarse portion is distributed across all of the electrodes and so can source or sink current to any of the electrodes. The coarse portion is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking a coarse amount of current to or from any one of the electrodes on the device. The fine portion of the current generation circuit preferably includes source and sink circuitry dedicated to each of the electrode on the device, which can comprise digital-to-analog current converters (DACs).

8. 发明申请

US20170021181A1 Timing Channel Circuitry for Creating Pulses in an Implantable Stimulator Device 审中-公开
标题翻译：用于在可植入的刺激装置中产生脉冲的定时通道电路
公开(公告)号：US20170021181A1
公开(公告)日：2017-01-26
申请号：US15289809
申请日：2016-10-10
申请人： Boston Scientific Neuromodulation Corporation
发明人： Paul J. Griffith , Goran N. Marnfeldt , Jordi Parramon
IPC分类号： A61N1/372 , A61N1/36
CPC分类号： A61N1/37264 , A61N1/36125 , A61N1/372 , A61N1/37252
摘要： Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.
摘要翻译：公开了一种用于控制可植入刺激器中的刺激电路的定时通道电路。定时通道电路包括可寻址存储器。所需脉冲的各个相位的数据使用不同数量的字存储在存储器中，包括表示相位中的字数的命令，存储在存储器中的下一相的下一个地址，以及脉冲宽度或当前阶段的持续时间，刺激电路的控制数据，脉冲幅度和电极数据。命令数据用于通过地址总线对当前阶段中的字进行寻址，哪些字被发送到用于刺激电路的控制寄存器。在当前阶段的脉冲宽度持续时间过去之后，存储的下一个地址用于访问存储在存储器中的下一个相位的数据。

9. 发明申请

US20150174419A1 Timing Channel Circuitry for Creating Pulses in an Implantable Stimulator Device 审中-公开
标题翻译：用于在可植入的刺激装置中产生脉冲的定时通道电路
公开(公告)号：US20150174419A1
公开(公告)日：2015-06-25
申请号：US14636380
申请日：2015-03-03
申请人： Boston Scientific Neuromodulation Corporation
发明人： Paul J. Griffith , Goran N. Marnfeldt , Jordi Parramon
IPC分类号： A61N1/372
CPC分类号： A61N1/37264 , A61N1/36125 , A61N1/372 , A61N1/37252
摘要： Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.
摘要翻译：公开了一种用于控制可植入刺激器中的刺激电路的定时通道电路。定时通道电路包括可寻址存储器。所需脉冲的各个相位的数据使用不同数量的字存储在存储器中，包括表示相位中的字数的命令，存储在存储器中的下一相的下一个地址，以及脉冲宽度或当前阶段的持续时间，刺激电路的控制数据，脉冲幅度和电极数据。命令数据用于通过地址总线对当前阶段中的字进行寻址，哪些字被发送到用于刺激电路的控制寄存器。在当前阶段的脉冲宽度持续时间过去之后，存储的下一个地址用于访问存储在存储器中的下一个相位的数据。

10. 发明授权

US10363422B2 Architectures for an implantable stimulator device having a plurality of electrode driver integrated circuits with shorted electrode outputs 有权
公开(公告)号：US10363422B2
公开(公告)日：2019-07-30
申请号：US15491492
申请日：2017-04-19
申请人： Boston Scientific Neuromodulation Corporation
发明人： Emanuel Feldman , Jordi Parramon , Paul J. Griffith , Jess Shi , Robert Tong , Goran Marnfeldt
IPC分类号： A61N1/36 , A61N1/05
摘要： Disclosed is a new architecture for an IPG having a master and slave electrode driver integrated circuits. The electrode outputs on the integrated circuits are wired together. Each integrated circuit can be programmed to provide pulses with different frequencies. Active timing channels in each of the master and slave integrated circuits are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other integrated circuit so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.

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