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1. 发明申请

US20080131982A1 Method Of Trimming Semiconductor Elements With Electrical Resistance Feedback 有权
标题翻译：使用电阻反馈修整半导体元件的方法
公开(公告)号：US20080131982A1
公开(公告)日：2008-06-05
申请号：US12027916
申请日：2008-02-07
申请人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
发明人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
IPC分类号： H01L21/02
CPC分类号： H01L28/20 , H01C17/267 , H01L22/22
摘要： A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion of the conductive material. By reducing the volume of the conductive material, its resistance is increased. The application of the voltage is ceased once the desired dimensions (and thus resistivity) of the conductive material is reached. The resulting semiconductor resistor element could have a fixed resistance, or could have a variable resistance (by using phase change memory material).
摘要翻译：使用电阻反馈来减少半导体电阻元件的体积的方法。在形成设置在一对电极之间的导电材料之后，向电极施加电压以产生通过导电材料的电流，足以加热和熔化掉导电材料的一部分。通过减小导电材料的体积，其电阻增加。一旦达到导电材料的所需尺寸（因此电阻率），电压的施加就会停止。所得到的半导体电阻元件可以具有固定电阻，或者可以具有可变电阻（通过使用相变存储器材料）。

2. 发明申请

US20060094197A1 Method of trimming semiconductor elements with electrical resistance feedback 有权
标题翻译：用电阻反馈修整半导体元件的方法
公开(公告)号：US20060094197A1
公开(公告)日：2006-05-04
申请号：US10983314
申请日：2004-11-04
申请人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
发明人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
IPC分类号： H01L21/20
CPC分类号： H01L28/20 , H01C17/267 , H01L22/22
摘要： A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion of the conductive material. By reducing the volume of the conductive material, its resistance is increased. The application of the voltage is ceased once the desired dimensions (and thus resistivity) of the conductive material is reached. The resulting semiconductor resistor element could have a fixed resistance, or could have a variable resistance (by using phase change memory material).
摘要翻译：使用电阻反馈来减少半导体电阻元件的体积的方法。在形成设置在一对电极之间的导电材料之后，向电极施加电压以产生通过导电材料的电流，足以加热和熔化掉导电材料的一部分。通过减小导电材料的体积，其电阻增加。一旦达到导电材料的所需尺寸（因此电阻率），电压的施加就会停止。所得到的半导体电阻元件可以具有固定电阻，或者可以具有可变电阻（通过使用相变存储器材料）。

3. 发明授权

US07351613B2 Method of trimming semiconductor elements with electrical resistance feedback 有权
标题翻译：用电阻反馈修整半导体元件的方法
公开(公告)号：US07351613B2
公开(公告)日：2008-04-01
申请号：US10983314
申请日：2004-11-04
申请人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
发明人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
IPC分类号： H01L21/82
CPC分类号： H01L28/20 , H01C17/267 , H01L22/22
摘要： A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion of the conductive material. By reducing the volume of the conductive material, its resistance is increased. The application of the voltage is ceased once the desired dimensions (and thus resistivity) of the conductive material is reached. The resulting semiconductor resistor element could have a fixed resistance, or could have a variable resistance (by using phase change memory material).
摘要翻译：使用电阻反馈来减少半导体电阻元件的体积的方法。在形成设置在一对电极之间的导电材料之后，向电极施加电压以产生通过导电材料的电流，足以加热和熔化掉导电材料的一部分。通过减小导电材料的体积，其电阻增加。一旦达到导电材料的所需尺寸（因此电阻率），电压的施加就会停止。所得到的半导体电阻元件可以具有固定电阻，或者可以具有可变电阻（通过使用相变存储器材料）。

4. 发明授权

US07790518B2 Method of trimming semiconductor elements with electrical resistance feedback 有权
标题翻译：用电阻反馈修整半导体元件的方法
公开(公告)号：US07790518B2
公开(公告)日：2010-09-07
申请号：US12027916
申请日：2008-02-07
申请人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
发明人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
IPC分类号： H01L21/82
CPC分类号： H01L28/20 , H01C17/267 , H01L22/22
摘要： A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion of the conductive material. By reducing the volume of the conductive material, its resistance is increased. The application of the voltage is ceased once the desired dimensions (and thus resistivity) of the conductive material is reached. The resulting semiconductor resistor element could have a fixed resistance, or could have a variable resistance (by using phase change memory material).
摘要翻译：使用电阻反馈来减少半导体电阻元件的体积的方法。在形成设置在一对电极之间的导电材料之后，向电极施加电压以产生通过导电材料的电流，足以加热和熔化掉导电材料的一部分。通过减小导电材料的体积，其电阻增加。一旦达到导电材料的所需尺寸（因此电阻率），电压的施加就会停止。所得到的半导体电阻元件可以具有固定电阻，或者可以具有可变电阻（通过使用相变存储器材料）。

5. 发明授权

US07403418B2 Word line voltage boosting circuit and a memory array incorporating same 有权
公开(公告)号：US07403418B2
公开(公告)日：2008-07-22
申请号：US11241582
申请日：2005-09-30
申请人： Ya-Fen Lin , Elbert Lin , Hieu Van Tran , Jack Edward Frayer , Bomy Chen
发明人： Ya-Fen Lin , Elbert Lin , Hieu Van Tran , Jack Edward Frayer , Bomy Chen
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C16/08
摘要： A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source. An adjacent word line, capacitively coupled to the first word line, is electrically connected to a second switch to a second voltage source. A sequencing circuit activates the first switch and the second switch such that the first word line is connected to the first voltage source, and the second word line is disconnected from the second voltage source. Then the sequencing circuit causes the first switch to disconnect the first word line from the first voltage source, and causes the second word line to be electrically connected to the second voltage source. The alternate switching of the connection boosts the voltage on the first word line, caused by its capacitive coupling to the second word line. A boosted voltage on the word line may be used to improve cycling and yield, where the memory cells of the array are of the floating gate type and erase through the mechanism of Fowler-Nordheim tunneling from the floating gate to a control gate which is connected to the word line.

6. 发明授权

US07050316B1 Differential non-volatile content addressable memory cell and array using phase changing resistor storage elements 有权
标题翻译：差分非易失性内容可寻址存储单元和阵列使用相变电阻存储元件
公开(公告)号：US07050316B1
公开(公告)日：2006-05-23
申请号：US10797207
申请日：2004-03-09
申请人： Ya-Fen Lin , Elbert Lin , Dana Lee , Bomy Chen , Hung Q. Nguyen
发明人： Ya-Fen Lin , Elbert Lin , Dana Lee , Bomy Chen , Hung Q. Nguyen
IPC分类号： G11C15/00
CPC分类号： G11C15/046 , G11C13/0004
摘要： A differential sensing content addressable memory cell without any word lines connected to the cells in the same row comprises a first bit line for supplying a first bit. A first storage element has a first phase change resistor for storing a first stored bit, which is connected in series with a first diode. The first storage element is connected to the first bit line. A second bit line supplies a second bit, with the second bit being an inverse of the first bit. A second storage element has a second phase change resistor for storing a second stored bit, which is connected in series with a second diode. The second storage element is connected to the second bit line. A match line is connected to the first and second storage elements for indicating whether a match occurred between the first bit and the first stored bit, and between the second bit and the second stored bit
摘要翻译：差分感测内容可寻址存储单元，没有连接到同一行中的单元的任何字线包括用于提供第一位的第一位线。第一存储元件具有第一相变电阻器，用于存储与第一二极管串联连接的第一存储位。第一存储元件连接到第一位线。第二位线提供第二位，第二位是第一位的倒数。第二存储元件具有用于存储与第二二极管串联连接的第二存储位的第二相变电阻器。第二存储元件连接到第二位线。匹配线连接到第一和第二存储元件，用于指示在第一位和第一存储位之间以及第二位和第二存储位之间是否发生匹配

7. 发明申请

US20070076489A1 Word line voltage boosting circuit and a memory array incorporating same 有权
公开(公告)号：US20070076489A1
公开(公告)日：2007-04-05
申请号：US11241582
申请日：2005-09-30
申请人： Ya-Fen Lin , Elbert Lin , Hieu Tran , Jack Frayer , Bomy Chen
发明人： Ya-Fen Lin , Elbert Lin , Hieu Tran , Jack Frayer , Bomy Chen
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C16/08
摘要： A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source. An adjacent word line, capacitively coupled to the first word line, is electrically connected to a second switch to a second voltage source. A sequencing circuit activates the first switch and the second switch such that the first word line is connected to the first voltage source, and the second word line is disconnected from the second voltage source. Then the sequencing circuit causes the first switch to disconnect the first word line from the first voltage source, and causes the second word line to be electrically connected to the second voltage source. The alternate switching of the connection boosts the voltage on the first word line, caused by its capacitive coupling to the second word line. A boosted voltage on the word line may be used to improve cycling and yield, where the memory cells of the array are of the floating gate type and erase through the mechanism of Fowler-Nordheim tunneling from the floating gate to a control gate which is connected to the word line.

8. 发明授权

US07763492B2 Method of making phase change memory device employing thermally insulating voids and sloped trench 有权
标题翻译：制造使用隔热空隙和倾斜沟槽的相变存储装置的方法
公开(公告)号：US07763492B2
公开(公告)日：2010-07-27
申请号：US11807131
申请日：2007-05-25
申请人： Bomy Chen
发明人： Bomy Chen
IPC分类号： H01L21/06
CPC分类号： H01L45/06 , G11C13/0004 , H01L27/2463 , H01L45/1226 , H01L45/1253 , H01L45/1293 , H01L45/144 , H01L45/16 , Y10S438/90
摘要： A phase change memory device, and method of making the same, that includes a trench formed in insulation material having opposing sidewalls that are inwardly sloping with trench depth. A first electrode is formed in the trench. Phase change memory material is formed in electrical contact with the first electrode. A second electrode is formed in electrical contact with the phase change memory material. Voids are formed in the insulation material to impede heat from the phase change memory material from conducting away therefrom. The voids are formed in pairs, with either a portion of the phase change memory material or the second electrode disposed between the voids.
摘要翻译：相变存储器件及其制造方法，其包括形成在绝缘材料中的沟槽，该沟槽具有向内倾斜的沟槽深度的相对的侧壁。第一电极形成在沟槽中。相变记忆材料形成为与第一电极电接触。形成与相变记忆材料电接触的第二电极。在绝缘材料中形成空隙以阻止相变记忆材料的热量远离导线。这些空隙成对地形成，其中一部分相变记忆材料或第二电极设置在空隙之间。

9. 发明授权

US07605092B2 Passive elements, articles, packages, semiconductor composites, and methods of manufacturing same 有权
标题翻译：被动元件，制品，封装，半导体复合材料及其制造方法
公开(公告)号：US07605092B2
公开(公告)日：2009-10-20
申请号：US11772080
申请日：2007-06-29
申请人： Bomy Chen , Long Ching Wang , Sychyi Fang
发明人： Bomy Chen , Long Ching Wang , Sychyi Fang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5389 , H01L28/10 , H01L28/91 , H01L2223/6677 , H01L2224/12105 , H01L2224/24137 , H01L2224/73267 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein.
摘要翻译：公开了与半导体制品相关联的系统和方法，包括在衬底上形成第一材料层，在限定第一层中的无源元件的区域内蚀刻沟槽，在沟槽的侧壁上形成金属区域，以及形成电介质区域聚合物材料在衬底上或衬底中。此外，示例性方法还可以包括在沟槽的侧壁上形成金属区域的区域，使得这些区域的平面条带部分形成无源元件的导电区域，该无源元件相对于主要平面基本上垂直地排列底物。其它示例性实施例可以包括与本文所阐述的创新的一个或多个方面一致的各种物品或方法，包括电容和/或感应方面，基于钛和/或钽的电阻方面，产品，通过工艺，封装和复合材料的产品。

10. 发明申请

US20070278471A1 Novel chalcogenide material, switching device and array of non-volatile memory cells 审中-公开
标题翻译：新型硫族化物材料，开关器件和非易失性存储器单元阵列
公开(公告)号：US20070278471A1
公开(公告)日：2007-12-06
申请号：US11443876
申请日：2006-05-30
申请人： Bomy Chen , Yin Yin Lin
发明人： Bomy Chen , Yin Yin Lin
IPC分类号： H01L29/06
CPC分类号： H01L27/2472 , G11C13/0004 , G11C13/0069 , G11C2013/008 , H01L27/2481 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/126 , H01L45/144
摘要： A novel chalcogenide material has a bulk composition which has a first material selected from the group of Si and Sn, a second material selected from the group of Sb, and a third material selected from the group of Te. The first material, second material, and third material are in a ratio of (Six or Sny) Sb2 Te5, where x is 1≦x≦5, and y is 0.5≦y≦2.0. The material can be used in a switch device, which includes a dielectric/heater layer having a first surface and a second surface opposite the first surface, and the material having a first surface and a second surface opposite the first surface; with the first surface of the material immediately adjacent to and in contact with the first surface of the dielectric/heater layer. A first electrical contact is on the second surface of the dielectric/heater layer. A second electrical contact is on the second surface of the phase changing chalcogenide material. A third electrical contact is on the second surface of the phase changing chalcogenide material, spaced apart from the second electrical contact. The switching device can be programmed such that the channel length separation between the second electrical contact and the third electrical contact on the phase changing chalcogenide material is changed to represent the desired state to be stored in the device. Finally, an array of the above described non-volatile memory cells can be formed in a dielectric/heater layer and the chalcogenide material.
摘要翻译：新型硫族化物材料具有本体组合物，其具有选自Si和Sn的第一材料，选自Sb的第二材料和选自Te组的第三材料。第一材料，第二材料和第三材料的比例为（Si x Si x Si y Sb y Sb 2 Sb 2 O 3），其中x是1 <= x <= 5，y是0.5 <= y <= 2.0。该材料可以用在开关装置中，其包括具有第一表面和与第一表面相对的第二表面的电介质/加热器层，并且该材料具有与第一表面相对的第一表面和第二表面; 其中材料的第一表面紧邻电介质/加热器层的第一表面并与其接触。电介质/加热器层的第二表面上具有第一电接触。第二个电触点位于相变硫族化物材料的第二个表面上。相变硫族化物材料的第二表面上的第三电接触与第二电触点间隔开。切换装置可以被编程为使得在相变硫属化物材料上的第二电接触和第三电接触之间的通道长度间隔被改变以表示要存储在设备中的期望状态。最后，可以在电介质/加热器层和硫族化物材料中形成上述非易失性存储单元的阵列。

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