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    • 3. 发明授权
    • Method for controlling CD during an etch process
    • 在蚀刻过程中控制CD的方法
    • US07029593B2
    • 2006-04-18
    • US10685032
    • 2003-10-14
    • Myeong-Cheol KimYong-Hoon KimJeong-Yun Lee
    • Myeong-Cheol KimYong-Hoon KimJeong-Yun Lee
    • G05D5/00
    • H01L22/20G03F1/36G03F1/80
    • A method for controlling CD of etch process defines difference between designed dimension and etched dimension as dimensional displacement and defines target value of the dimensional displacement. A plurality of samples are prepared in each group having different exposure ratios. The plurality of samples of each group are etched until etch end point is detected and then over-etched for uniform time interval after detecting the etch end point. Using etch end point and over-etch time, correlation function of the over-etch time to the etch end point time is determined and the over-etch time to the etch end point is determined using the correlation function.
    • 用于控制蚀刻工艺的CD的方法将设计尺寸和蚀刻尺寸之间的差异定义为尺寸位移并且定义尺寸位移的目标值。 在具有不同曝光比的每个组中制备多个样品。 每个组的多个样品被蚀刻直到检测到蚀刻终点,然后在检测到蚀刻终点之后过度蚀刻均匀的时间间隔。 使用蚀刻终点和过蚀刻时间,确定到蚀刻终点时间的过蚀刻时间的相关函数,并且使用相关函数确定蚀刻终点的过蚀刻时间。
    • 6. 发明授权
    • Photo-mask having exposure blocking region and methods of designing and fabricating the same
    • 具有曝光阻挡区域的光掩模及其设计和制造方法
    • US07560198B2
    • 2009-07-14
    • US11145985
    • 2005-06-07
    • Il-Yong JangSeong-Woon ChoiSeong-Yong MoonJeong-Yun LeeSung-Hoon Jang
    • Il-Yong JangSeong-Woon ChoiSeong-Yong MoonJeong-Yun LeeSung-Hoon Jang
    • G03F1/00
    • G03F1/36
    • A photo-mask has a main mask pattern in a main region, a density correcting pattern in a peripheral region, and an exposure blocking pattern interposed between the main mask pattern and density correcting pattern. The exposure blocking pattern is configured to prevent the density correcting pattern from being transcribed to a wafer. The photo-mask is made by providing mask substrate on which a mask layer and a photoresist layer are disposed, providing design data that specifies at least the main mask pattern, and using the design data to derive exposure data that controls the exposure of the photoresist layer. The exposure data includes information that specifies the exposure blocking pattern, the portion of the peripheral region to be occupied by the density correcting pattern, and the pattern density of that portion of the peripheral region to be occupied by the density correcting pattern.
    • 光掩模在主区域中具有主掩模图案,在周边区域中具有浓度校正图案,以及插入在主掩模图案和密度校正图案之间的曝光阻挡图案。 曝光阻挡图案被配置为防止将密度校正图案转录到晶片。 光掩模是通过提供其上设置有掩模层和光致抗蚀剂层的掩模基板制成的,提供至少指定主掩模图案的设计数据,并且使用该设计数据来导出控制光致抗蚀剂曝光的曝光数据 层。 曝光数据包括指定曝光阻挡图案的信息,由密度校正图案占据的外围区域的部分以及由密度校正图案占据的外围区域的那部分的图案密度。
    • 8. 发明授权
    • Method of manufacturing semiconductor device that includes forming self-aligned contact pad
    • 包括形成自对准接触垫的半导体器件的制造方法
    • US07253099B2
    • 2007-08-07
    • US10957305
    • 2004-09-30
    • Jae-Hee HwangJeong-Yun LeeTae-Ryong KimYong-Hyeon Park
    • Jae-Hee HwangJeong-Yun LeeTae-Ryong KimYong-Hyeon Park
    • H01L21/4763
    • H01L27/10888H01L21/31144H01L21/76897H01L27/10855
    • According to some embodiments, a gate electrode structure including a gate electrode stack and a spacer, and source/drain region are formed on a semiconductor substrate. A first interlayer insulating layer having a thickness greater than that of the gate electrode structure is formed on the semiconductor substrate. On the first interlayer insulating layer, an etch inducing and focusing mask extending in a same direction as a length direction of the gate electrode structure and covering the gate electrode structure is formed. A second interlayer insulating layer is formed on the first interlayer insulating layer. A photoresist pattern is formed on the second interlayer insulating layer. The second interlayer insulating layer and the first interlayer insulating layer are sequentially etched using the photoresist pattern as an etch mask, thereby forming a SAC hole. A conductive material is used to fill in the SAC hole to form a SAC pad.
    • 根据一些实施例,在半导体衬底上形成包括栅电极堆叠和间隔物的栅电极结构以及源/漏区。 在半导体衬底上形成厚度大于栅电极结构的第一层间绝缘层。 在第一层间绝缘层上,形成沿与栅电极结构的长度方向相同的方向延伸且覆盖栅电极结构的蚀刻诱导和聚焦掩模。 在第一层间绝缘层上形成第二层间绝缘层。 在第二层间绝缘层上形成光刻胶图形。 使用光致抗蚀剂图案作为蚀刻掩模,依次蚀刻第二层间绝缘层和第一层间绝缘层,从而形成SAC孔。 使用导电材料填充SAC孔以形成SAC垫。